CS 320 Unit 10 Pipelining the CPU

CS 320 Unit 10 Pipelining the CPU - CS 320 Computer...

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Unformatted text preview: CS 320 Computer Architecture Unit 10 Pipelining the CPU Spring 2008 Furman Haddix, Ph.D. Assistant Professor Minnesota State University, Mankato Pipelining the CPU 2 Unit 10 Objectives • Understanding Pipelining and Superscalar • Understanding Pipelining the Datapath – Data Buses, Shifter/ALU and Register File • Understanding Pipelining the Microinstruction Path (Control Unit) – Instruction Buses, Decoders, Control Store, Microinstruction Registers • Issues of RAM versus ROM • Compiled Control Store Addresses versus Look up Control Store Addresses • Converting Mic-2 Microcodes to Mic-4 • Operation of the Mic-4 • FSM Implementation of ALU • Text, Sns. 2.1.5, 4.4 Pipelining the CPU 3 Instruction-Level Pipelining • Some CPUs divide the fetch-decode-execute cycle into smaller steps, e.g., multiple cycle processor • These smaller steps can often be executed in parallel to increase throughput. • Such parallel execution is called instruction-level pipelining . • Instruction-level pipelining is based on the idea that different parts of the CPU are used for different phases or stages of a computation. If we can have parallelism between these different parts or units of the CPU, more instructions can be processed in the same time Pipelining the CPU 4 Parallelism in Computing • Processor-level parallelism – Data parallelism – Instruction parallelism • Thread-level parallelism – Virtual and Physical, Single and Multiple Processors and Cores • Instruction-level parallelism – Pipelining – Superscalar • This Unit is about Instruction-level parallelism – Single processor – Single process – Single thread – Parallelism between instructions • Parallelism across stages – Pipelining • Parallelism within stages – Superscalar • Future units will discuss processor-level parallelism and thread-level parallelism Pipelining the CPU 5 Turnaround and Throughput • Turnaround with respect to instructions is the time it takes to process an instruction from start to finish • Throughput is the total amount of work done in a time interval • Instruction-level pipelining is about increasing the throughput of instructions, thereby decreasing the time to complete a job, or set of jobs • One way to decrease turnaround for an instruction is to increase the clock speed. This will also decrease the time to complete a job, or set of jobs. • Although pipelining doesn’t decrease turnaround for an instruction it does decrease the turnaround for a sequence of instructions, e.g., program Pipelining the CPU 6 Pipelining • Two alternatives for a three instruction program – sequential – parallel (two-stage pipeline) • Objective with pipelining is to start processing second instruction before finishing first fetch 1 fetch 2 decode 1 fetch 3 decode 2 execute 1 decode 3 execute 3 execute 2 fetch 1 fetch 2 decode 2 decode 1 execute 2 execute 1 fetch 3 decode 3 execute 3 Pipelining the CPU 7 Instruction-Level Pipelining...
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This note was uploaded on 06/09/2008 for the course CS 320 taught by Professor Furmanhaddix during the Spring '08 term at Minnesota State University, Mankato.

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CS 320 Unit 10 Pipelining the CPU - CS 320 Computer...

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