CS 320 Unit 13 Overview of Instruction Set Architectures

CS 320 Unit 13 Overview of Instruction Set Architectures -...

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Unformatted text preview: Computer Architecture Unit 13 Overview of Instruction Set Architectures Spring 2008 Furman Haddix, Ph.D. Assistant Professor Minnesota State University 2 Instruction Set Architecture Level 3 Unit 13 Objectives • Instruction Set Architecture Overview – Instruction Set Architectures (ISA) – Memory models – Datatypes – Registers – Instruction Formats – Instruction Types • Text, Chapter 5 4 Instruction Set Architecture • What determines an Instruction Set Architecture? • What higher-level language features do the software guys want? • What component functionality do the hardware guys want? • Is it backwards compatible? • Will it be price-competitive for its intended purpose? 5 Where the ISA Level Fits C++, Java Assembly C++, Java programs compiled to machine language Assembly programs assembled to machine language Computer Computer The ISA level is the interface between the computer and its applications, such as operating systems, compilers, and application programs. Here, computer is used to mean the sum of the physical components, e.g., hardware, and its firmware, e.g, microprogram. The only language that a computer recognizes at run-time is its machine language or Instruction Set Architecture (ISA) 6 What is an Instruction Set • What are the modes of operation – E.g., kernel mode, user mode. • Identification of valid instructions/formats – What is processible by the computer under normal processing? • Definition of instruction functionality – What is the processing that implements the instruction? • Definition of exception/error handling – How are exceptions to valid instructions/formats processed? – How are execution errors handled? 7 ISA Modes • User (Our Emphasis) – Applications programming – Applications execution – Word, Excel – Applets – … • Kernel – Systems programming – Direct cache manipulation – Direct peripheral device commands – Systems library creation 8 Classification of Automatic Computer Architectures • Three principal dimensions, not completely independent • Number of Operands for Binary ALU Ops – 0 Stack machine Never load-store Always CISC – 1 Accumulator machines Never load-store Usually CISC – 2 Two address machines Less likely to be load-store and/or RISC – 3 Three address machines More likely to be load-store and RISC • Load-store – Only memory operations are Load or Store – Memory-ALU operations allowed • RISC/CISC – Reduced Instruction Set Computers • Machine language instruction executed as one microinstruction • Always Load-store; converse is not true – Complex Instruction Set Computers • Machine language instruction executed as one or more microinstructions – Reality is … no machine is 100% RISC 9 Very Long Instruction Words (VLIW) • Some authors consider this the next class of Architecture....
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This note was uploaded on 06/09/2008 for the course CS 320 taught by Professor Furmanhaddix during the Spring '08 term at Minnesota State University, Mankato.

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CS 320 Unit 13 Overview of Instruction Set Architectures -...

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