CS 320 Unit 15 RISC Architectures

CS 320 Unit 15 RISC Architectures - Unit 15 RISC...

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Unit 15 RISC Instruction Set Architectures CS 320 Computer Architecture Spring 2008 Minnesota State University Furman Haddix, Assistant Professor
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Unit 15 RISC Architectures Objectives Unit 14 Complex Instruction Set Computing (CISC) Architectures Java Virtual Machine Intel Architecture-32 Unit 15 Reduced Instruction Set Computing (CISC) Architectures UltraSPARC III PIC Comparison of RISC/CISC Instruction Set Architectures Unit 16 Very Long Instruction Word (VLIW Architecture) VLIW Example: Intel Architecture-64 (IA-64 Itanium) VLIW/RISC Comparison Text, Chapter 5
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12-bit PIC Computation Model Data has three sources: W, f, or k. W is the Accumlator (Register) f is a logical register (RAM address) {0-31} k is an 8-bit immediate operand Instruction Formats bit 11 10 9 8 7 6 5 4 3 2 1 0 F1 OpCode k = literal F2 OpCode f = address d F3 OpCode f = address F4 OpCode
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12-bit PIC Computation Model Data values can be stored in several places: W is the Accumulator (Register) f is a logical register (RAM address) {0-31} k is an 8-bit immediate operand stored in ROM PC is a separate location IR is a separate location 8 (13-bit) locations in return address stack Program memory is a ROM, which requires a programmer (h/w) to rewrite (EEPROM).
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PIC Datapath 1 bus effectively serves as internal bus and memory bus 1 bus with immediate operands (literals) multiplexed in from IR Program memory is EEPROM requires additional Accumulator Microarchitecture 1-address All ALU ops are implicitly ACC ACC op Opd Opd ACC op Opd Since register W (accumulator) can be read to and written from bus, need special hardware No MAR, MDR
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PIC Instruction Set OpCode Operand Mnemonic Description RTL E 8u ANDLW k AND literal and W W k AND W 9 8u CALL k Call direct address k TOS PC + 1 PC k A 8u GOTO k Go to direct address k PC k D 8u IORLW k OR literal and W W k OR W C 8u MOVLW k Move literal to W W k 8 8u RETLW k Return with literal in W PC TOS W k F 8u XORLW k XOR literal and W W k XOR W 1C 5u, 1u ADDWF f, d Add W and f d W + f 14 5u, 1u ANDWF f, d AND W and f d W AND f 06 5u CLRF f Clear f f 0 040 CLRW Clear W W 0 W, k, f, d definitions on next slide
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OpCode Operand Mnemonic Description RTL 24 5u, 1u COMF f, d Complement f d NOT f 0C 5u, 1u DECF f, d Decrement f d f - 1 2C 5u, 1u DECFSZ f, d Decrement f, skip if 0 d f - 1 28 5u, 1u INCF f, d Increment f d f + 1 3C 5u, 1u INCFSZ f, d Increment f, skip if 0 d f + 1 10 5u, 1u IORWF f, d OR W and f d W OR f 20 5u, 1u MOVF f, d Move f d f 02 5u MOVWF f Move W to f f W 000 NOP No operation W – Accumulator (or Working register) k – 8-bit literal (unsigned integer) f – Register file (RAM) address (4 bits for arithmetic, 5 bits for load, store d – Destination flag: 0, if W; 1, if f. DECFSZ, INCFSZ if 0, reset instruction register (NOP)
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This note was uploaded on 06/09/2008 for the course CS 320 taught by Professor Furmanhaddix during the Spring '08 term at Minnesota State University, Mankato.

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CS 320 Unit 15 RISC Architectures - Unit 15 RISC...

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