CS 320 Unit 16 VLIW Architecture

CS 320 Unit 16 VLIW Architecture - Unit 16 VLIW Instruction...

Info iconThis preview shows pages 1–9. Sign up to view the full content.

View Full Document Right Arrow Icon
Unit 16 VLIW Instruction Set Architecture CS 320 Computer Architecture Spring 2008 Furman Haddix, Assistant Professor Minnesota State University
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Unit 16 VLIW Architecture Objectives VLIW Example: IA-64 Overview Register Stack Frames Explicit Parallelism (Bundling) Predication Speculative Loads Conclusions Text, Chapter 5
Background image of page 2
The IA-64 Architecture: Explicitly Parallel Instruction Computing Load/Store 64-bit addresses and registers 64 general purpose registers Principally one 41-bit Instruction Format 14-bit opcode (4-bit major opcode) 7-bit destination register 2 7-bit source registers 6-bit predicate register Instruction Bundling Register Stack Frames
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Itanium Architecture The Itanium (IA-64) has only a 10-stage pipeline branch misprediction can cause 9 cycles of bubbles The Itanium, having a RISC core, supports only one form of memory addressing: register indirect addressing with optional post increment. Itanium uses Register Stack Frame to reduce penalty for context switch for function calls similar to UltraSPARC Register Windows Note that the Itanium also supports register direct and immediate addressing modes; however, these do not access memory.
Background image of page 4
Itanium Physical Registers Register Name Register Type gr0 Zero gr1 - gr127 General-purpose 64-bit registers f0 +0.0 f1 +1.0 f2 - f127 Floating-point registers p0 - p1 True & False (respectively) p2 - p63 Predicate registers (1-bit) b0 - b7 Branch registers ar0 - ar127 Application registers cr0 - cr127 Control registers
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Itanium Register Stack Frames Itanium has 128 physical general purpose registers Each process has 64 general purpose registers visible Registers gr0-gr31 (r0-r31) are static (global) Logical registers r32-r63 are from register stack frame – all may not be assigned Register stack frame registers are renamed from physical registers gr32-gr127 Each process has input, local, and output registers allocated based on its needs, specified by alloc verb. Input registers are determined by output registers of calling process (ins i = outs i-1 ) Local registers are determined by size of local (sol) - number of input registers (locs = sol – ins) Output registers are determined by size of frame (sof) – sol (outs = sof – sol)
Background image of page 6
Instruction Bundling for the Itanium 3 instructions plus 5-bit template form bundle Very Long Instruction Word (VLIW) of 128 bits Bundles can be chained together Template contains parallelizing instructions from the compiler/assembler on what can be executed in parallel Moving parallelization from hardware at execution time to compiler at compile time Less hardware Compiler has time for optimization Done once at compile time rather than at every execution
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
IA-64 Instruction Set 14-bit OpCode 7-bit Source Register 7-bit Source Register 7-bit Destination Register 6-bit Predicate Register 41-bit Instruction (4-address): Bundle (VLIW):
Background image of page 8
Image of page 9
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 06/09/2008 for the course CS 320 taught by Professor Furmanhaddix during the Spring '08 term at Minnesota State University, Mankato.

Page1 / 63

CS 320 Unit 16 VLIW Architecture - Unit 16 VLIW Instruction...

This preview shows document pages 1 - 9. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online