# hw9sol - the delay of the first stage is 6ns and the delay...

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ECE 2030F Homework 9 Solution (Total 50 points) 1. (Mano/Kime 3 rd ed problem 10-12 a,b): (20 points) (a) (10 points) The maximum total delay from register file to register file is 2+1+3+4+4 = 14ns, so the maximum clock frequency is 1/14ns = 71.4MHz. (b) (10 points) When the datapath is pipelined using stages, the clock frequency is limited by the longest delay of all pipeline stages. Hence, the components should be combined in such a way that the maximum delays of all stages are approximately equal. The best solution for 3-stage pipelined datapath is to combine components A, B and C into one stage, and put D and E in stage 2 and 3, respectively. In this case,
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Unformatted text preview: the delay of the first stage is 6ns, and the delay of the second or the third stage is 4ns. Therefore, the maximum clock frequency is 1/6ns = 166.7MHz. 2. (Mano/Kime 3 rd ed problem 10-13): (30 points) (a) (10 points) Since there are 6 opcode bits, the maximum number of operations that can be specified is 2 6 = 64. (b) (10 points) There are 2 6 = 64 registers that can be addressed because each register fields is 6 bits long. (c) (10 points) The immediate field of length 14 bits provides the range of unsigned immediate operands from 0 to 2 14-1, that is, from 0 to 16383....
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