Unformatted text preview: the delay of the first stage is 6ns, and the delay of the second or the third stage is 4ns. Therefore, the maximum clock frequency is 1/6ns = 166.7MHz. 2. (Mano/Kime 3 rd ed problem 1013): (30 points) (a) (10 points) Since there are 6 opcode bits, the maximum number of operations that can be specified is 2 6 = 64. (b) (10 points) There are 2 6 = 64 registers that can be addressed because each register fields is 6 bits long. (c) (10 points) The immediate field of length 14 bits provides the range of unsigned immediate operands from 0 to 2 141, that is, from 0 to 16383....
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 Fall '07
 WOLF
 Frequency, Central processing unit, Processor register, Instruction pipeline, maximum clock frequency

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