fa07-lw-s1

# fa07-lw-s1 - ECE 2030 B 12:00pm 4 problems 4 pages Problem...

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ECE 2030 B 12:00pm Computer Engineering Fall 2007 4 problems, 4 pages Exam One Solutions 19 September 2007 1 Problem 1 (3 parts, 30 points) Incomplete Circuits For each partial switch circuit below, complete the complementary switching network so the circuit contains no floats or short. Also write the Boolean expression computed by the completed circuit. Assume the inputs and their complements are available. OUTx = ) ( ) ( E D C B A + + OUTy = E D C B A + ) ( OUTz = B A + Out y B C F A E D Out x A C B E D Out z B A A B CD E A B C D E A B

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ECE 2030 B 12:00pm Computer Engineering Fall 2007 4 problems, 4 pages Exam One Solutions 19 September 2007 2 Problem 2 (2 parts, 26 points) Mixed Logic Design Implement the following expressions using gates to minimize total transistors (switches) required. Use proper mixed logic design technique. Only multi-input OR and NOT gates may be used. Do not simplify the expression. Part A (11 points) F E D C B A OUT X + + = ) ( ) ( # switches = 8 + 3 × 6 + 6 × 2 = 8 + 18 + 12 = 38 Part B (15 points) ) ) ) ( ( ) (( ) ) ( ( F E D C B A C B A A OUT Y + + +
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## This note was uploaded on 06/17/2008 for the course ECE 2030 taught by Professor Wolf during the Fall '07 term at Georgia Tech.

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fa07-lw-s1 - ECE 2030 B 12:00pm 4 problems 4 pages Problem...

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