fa07-lw-s3 - ECE 2030 12:00pm 4 problems, 6 pages Problem 1...

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ECE 2030 12:00pm Computer Engineering Fall 2007 4 problems, 6 pages Exam Three 28 November 2007 1 Problem 1 (3 parts, 30 points) Memory Systems Part A (12 points) Consider a 64Mbit DRAM chip organized as 2 million addresses of 32-bit words . Assume both the DRAM cell and the DRAM chip are square. The column number and offset concatenate to form the memory address. Using the organization approach discussed in class, answer the following questions about the chip. Express all answers in decimal (not powers of two) . number of columns K 8 2 2 13 26 = = number of words per column 256 2 2 / 2 8 5 13 = = column decoder required ( n to m ) 13 to 2 13 = 13 to 8K decoder type of mux required ( n to m ) 256 to 1 number of address lines in column number 13 number of address lines in column offset log(256) = 8 Part B (10 points) Consider an two gigabyte memory system with 1 billion addresses of 16-bit words using a 16 million address by 8-bit word memory DRAM chip. word address lines for memory system 30 chips needed in one bank 2 2 / 2 3 4 = chips banks for memory system 64 2 2 / 2 6 24 30 = = memory decoder required ( n to m ) 6 to 64 decoder DRAM chips required 2x64 = 128 Part C (8 points) Design a 16 million address by 8 bit memory system with four 8M x 4 memory chips. Label all busses and indicate bit width . Assume R/W is connected and not shown here. Use a bank decoder if necessary. 8M x 4 D0 D1 D2 D3 ADDR CS 8M x 4 D0 D1 D2 D3 ADDR CS 8M x 4 D0 D1 D2 D3 ADDR CS ADDR 24 MSEL D0 D1 D2 D3 8M x 4 D0 D1 D2 D3 ADDR CS D4 D5 D6 D7 23 A22:0 1 to 2 decoder EN O0 O1 S A23 23 23 23 23
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ECE 2030 12:00pm Computer Engineering
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fa07-lw-s3 - ECE 2030 12:00pm 4 problems, 6 pages Problem 1...

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