fa07-sw-s3

# fa07-sw-s3 - ECE 2030 10:00pm 4 problems, 4 pages Problem 1...

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ECE 2030 10:00pm Computer Engineering Fall 2007 4 problems, 4 pages Exam Three Solutions 28 November 2007 1 Problem 1 (3 parts, 30 points) Memory Systems Part A (12 points) Consider a four Gbit DRAM chip organized as 128 million addresses of four byte words . Assume both the DRAM cell and the DRAM chip are square. The column number and offset concatenate to form the memory address. Using the organization approach discussed in class, answer the following questions about the chip. Express all answers in decimal (not powers of two) . number of columns sqrt(4G) = sqrt(2 32 ) = 2 16 = 64K number of words per column 64K / 32 = 2 16 /2 5 = 2 11 = 2K column decoder required ( n to m ) 16 to 64K type of mux required ( n to m ) 2K to 1 number of address lines in column number 16 number of address lines in column offset 11 Part B (10 points) Consider an eight megabyte memory system with 1 million addresses of 8 byte words using a 256 thousand address by 16 bit word memory DRAM chip. word address lines for memory system 1M address = 2 20 = 20 address lines chips needed in one bank 8 bytes / 2 byte = 4 chips/ bank banks for memory system 1 M / 256K = 2 20 / 2 18 = 2 2 = 4 banks memory decoder required ( n to m ) 2 to 4 DRAM chips required 4 banks x 4 chips/bank = 16 chips Part C (8 points) Design a 32 million address by 4 bit memory system with four 8M x 4 memory chips. Label all busses and indicate bit width

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## fa07-sw-s3 - ECE 2030 10:00pm 4 problems, 4 pages Problem 1...

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