fa06-sw-s1 - ECE 2030 B 1:00pm 4 problems, 4 pages Problem...

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ECE 2030 B 1:00pm Computer Engineering Fall 2006 4 problems, 4 pages Exam One Solution 20 September 2006 1 Problem 1 (3 parts, 30 points) Incomplete Circuits For each partial switch circuit below, complete the complementary switching network so the circuit contains no floats or short. Also write the Boolean expression computed by the completed circuit. Assume the inputs and their complements are available. Out x A C B DE A B D CE Out y A B E C D C A B D E Out z A C B D A C B D OUTx = E C D B A + OUTy = C E D B A + + ) ( OUTz = ) ( ) ( D B C A + +
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ECE 2030 B 1:00pm Computer Engineering Fall 2006 4 problems, 4 pages Exam One Solution 20 September 2006 2 Problem 2 (2 parts, 20 points) Mixed Logic Design Implement the following expressions using gates to minimize total transistors (switches) required. Where two expressions are specified for a single part, your implementation should provide both outputs. Use proper mixed logic design technique. Any combination of multi-input input AND, OR, NAND, NOR, and NOT gates may be used. Do not simplify the expression.
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This note was uploaded on 06/17/2008 for the course ECE 2030 taught by Professor Wolf during the Fall '07 term at Georgia Tech.

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fa06-sw-s1 - ECE 2030 B 1:00pm 4 problems, 4 pages Problem...

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