fa06-sw-s3 - ECE 2030 1:00pm 4 problems 4 pages Problem 1(2...

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ECE 2030 1:00pm Computer Engineering Fall 2006 4 problems, 4 pages Exam Three Solutions 29 November 2006 1 Problem 1 (2 parts, 24 points) Counters Part A (12 points) Design a toggle cell using transparent latches and basic gates. Use an icon for the latch. Your toggle cell should have an active high toggle enable input TE , and an active low clear input -Clear , clock inputs Φ 1 and Φ 2 , and an output Out . The - Clear signal has precedence over TE . Label all signals. In Out En Latch In Out En Latch TE Out CLR Φ 1 Φ 2 Part B (12 points) Now combine these toggle cells to build a divide by seven counter. Your counter should have an external clear, external count enable, and three count outputs O 2 , O 1 , O 0 . Use any basic gates (AND, OR, NAND, NOR, & NOT) you require. Assume clock inputs to the toggle cells are already connected. Your design should support multi-digit systems. O 0 O 1 O 2 Ext Clr Ext CE TE Out Clr TE Out Clr TE Out Clr
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ECE 2030 1:00pm Computer Engineering Fall 2006 4 problems, 4 pages Exam Three Solutions 29 November 2006 2 Problem 2 (2 parts, 18 points) Datapath Elements Part A (9 points) Consider the following input and output values for a shift operation. Determine the shift type and amount required to achieve the listed transformation. There are no overflows.
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This note was uploaded on 06/17/2008 for the course ECE 2030 taught by Professor Wolf during the Fall '07 term at Georgia Tech.

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fa06-sw-s3 - ECE 2030 1:00pm 4 problems 4 pages Problem 1(2...

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