fa04-sw-s3

# fa04-sw-s3 - ECE 2030 1:00pm 4 problems 4 pages Problem 1(2...

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ECE 2030 1:00pm Computer Engineering Fall 2004 4 problems, 4 pages Exam Three Solutions 17 November 2004 1 Problem 1 (2 parts, 24 points) Counters Part A (12 points) Design a toggle cell using only two transparent latches, two 2-to-1 muxes, and an inverter. Use icons for the latch and mux. Your toggle cell should have an active high toggle enable input TE , and an active low clear input -Clear , clock inputs Φ 1 and Φ 2 , and an output Out . The - Clear signal has precedence over TE . Label all signals. In Out En Latch In Out En Latch I 0 I 1 S Out I 0 I 1 S Out TE CLR Φ 1 Φ 2 “0” Out Part B (12 points) Now combine these toggle cells to build a divide by five counter. Your counter should have an external clear, external count enable, and three count outputs O 2 , O 1 , O 0 . Use any basic gates (AND, OR, NAND, NOR, & NOT) you require. Assume clock inputs to the toggle cells are already connected. Your design should support multi-digit systems. CEOut Clr Toggle CEOut Clr Toggle CEOut Clr Toggle O 0 O 1 O 2 Max Count Ext. CE Ext. CLR

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ECE 2030 1:00pm Computer Engineering Fall 2004 4 problems, 4 pages Exam Three Solutions 17 November 2004 2 Problem 2 (3 parts, 26 points) Memory Systems Part A (10 points) Consider a 256 Mbit DRAM chip organized as 64 million addresses of 4 bit words . Assume both the DRAM cell and the DRAM chip are square. The column number and
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## This note was uploaded on 06/17/2008 for the course ECE 2030 taught by Professor Wolf during the Fall '07 term at Georgia Tech.

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fa04-sw-s3 - ECE 2030 1:00pm 4 problems 4 pages Problem 1(2...

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