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hw3solutions - F a b c d e = a b c d e a b c d e F 28...

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GEORGIA INSTITUTE OF TECHNOLOGY SCHOOL of ELECTRICAL and COMPUTER ENGINEERING ECE 2030 Fall 2005 Problem Set #3 SOLUTION Assigned: 19-Sep-05 Due Date: 23-Sep-05 Problem 1 (4 pts): Implement the following using a mixed–logic design methodology. All gates must either have all inputs bubbled or no inputs bubbled. Be sure that all bubbles are paired. Do not assume that the compliment of inputs are available. Do not simplify the expressions. Also determine the number of transistors used by your design. (a) Implement the following expression using 2-input NOR gates and NOT gates. F = A ( B + C ) + DE A B C E D F 24 transistors (b) Implement the following expression using 2-input NOR gates and NOT gates. F ( a, b, c, d, e ) = a ( b + c ) + d e a b c d e F 28 transistors (c) Implement the following expression using 2-input NAND gates and NOT gates.
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Unformatted text preview: F ( a, b, c, d, e ) = a ( b + c ) + d e a b c d e F 28 transistors (d) Implement the following expression using 2-input NAND gates and NOT gates. F = ( a ⊕ b ) ⊕ c F c b a b a c 32 transistors Problem 2 (2 pts): Express the function computed by this circuit. A B C F F = ( A + B )( CB ) Problem 3 (2 pts): Express the function computed by this circuit. out a b c f g d e F = a ( bc )( d + e ) + ( ( d + e ) + ( f g ) ) Problem 4 (2 pts): This logic circuit is shown using mixed-logic format only using NAND gates. Redraw the circuit using mixed-logic format but using NAND and NOR gates to eliminate the need for inverters. a b c d f g e out...
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