ee101_hw5_sol

# Ee101_hw5_sol - EE 101 Homework 5 Redekopp Name_Solutions Due Score Show work to get full credit Remember use on only one side of the paper and

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1 EE 101 Homework 5 Redekopp Name: ___Solutions______________________________ Due: Score: ________ Show work to get full credit. Remember, use on only one side of the paper and staple them together. Only use a calculator to CHECK your work, not to DO your work. 1) (36 pts.) Design (create one schematic drawing for) each of the following single or multiple output logic functions using the building blocks listed below for each problem along with a NAND gate for each output bit. a. F 1 = WXYZ (0,3,6,7,10,12,14) (20 pts.) F 0 = WXYZ (1,4,7,13,15) Using (2) 3-to-8 decoders each w/ active-low outputs and 2 enables: 1 active high enable (G1) and 1 active-low (/G2). Besides the 3-to-8 decoders and the NAND gates to implement each output bit, you should not need any additional gates. In general, an n-input function can be built with an n-to-2 n decoder. Thus we need a 4-to- 16 decoder. So first build a 4-to-16 decoder, then use it to OR together minterms. Since the outputs are active low, NAND together minterms. /Y0 /Y1 /Y2 /Y3 /Y4 /Y5 /Y6 /Y7 A0 A1 A2 3-to-8 Decoder G1 /G2 /Y0 /Y1 /Y2 /Y3 /Y4 /Y5 /Y6 /Y7 /G2 /O0 /O1 /O2 /O3 /O4 /O5 /O6 /O7 /O8 /O9 /O10 /O11 /O12 /O13 /O14 /O15 W W 0 1 X Y Z X Y Z F0 F1 Equivalent to 7-input NAND (We can’t draw a 7-input NAND w/ drawing program). Same is true for F1.

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2 b. G = Π ABCD (1,2,5,6,7,9,10,13,14,15) (16 pts.) Using (5) 2-to-4 decoder each w/ (1) active-low enable and active-low outputs A B /D0 /D1 /D2 /D3 /E A B /D0 /D1 /D2 /D3 /E A B /D0 /D1 /D2 /D3 /E A B /D0 /D1 /D2 /D3 /E A B (MSB) /D0 /D1 /D2 /D3 /E A B 0 D C D C D C D C /O0 /O1 /O2 /O3 /O4 /O5 /O6 /O7 /O8 /O9 /O10 /O11 /O12 /O13 /O14 /O15 G Equivalent to 6-input NAND (We can’t draw a 6-input NAND w/ drawing program)
3 2) (8 pts.) Examine the decoder on the attached page: Label the enable with E or /E depending on whether it is active high or low. You must figure out which output corresponds to which gate based on the gate connections. Then label the outputs appropriately using Y 0 Y 1 Y 2 Y 3 or /Y 0 /Y 1 /Y 2 /Y 3 depending on whether they are active high or low.

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## This note was uploaded on 06/23/2008 for the course EE 101 taught by Professor Redekopp during the Fall '06 term at USC.

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Ee101_hw5_sol - EE 101 Homework 5 Redekopp Name_Solutions Due Score Show work to get full credit Remember use on only one side of the paper and

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