AppendixAUnit8_3Sol

AppendixAUnit8_3Sol - 8.3. Unit 3 Decoders, Encoder,...

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329 8.3. Unit 3 – Decoders, Encoder, Multiplexers, Demultiplexers, Adders and Comparators 1. a. F = C B A , , ) 7 , 6 , 4 , 2 ( = ,, (0,1,3,5) ABC b. F = Z Y X , , ) 6 , 4 , 2 , 0 ( Note: Notice this function is really equal to Z’ (True anytime Z = 0). Thus, if we had a 1-to-2 decoder I could implement the function as follows: /Y0 /Y1 /Y2 /Y3 /Y4 /Y5 /Y6 /Y7 A0 A1 A2 3-to-8 Decoder G1 /G2 A B C m0' m1' m2' m3' m4' m5' m6' m7' F 0 1 /Y0 /Y1 /Y2 /Y3 /Y4 /Y5 /Y6 /Y7 X Y Z F 1 0 D 0 D 1 A E Z 1 F
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330 c. F = Z Y X W , , , ) 15 , 13 , 11 , 8 , 7 , 4 , 2 , 1 ( Link m1’, m2’, m4’, m7’, m8’, m11’, m13’, and m15’ with a 8-input NAND gate, and the output of this NAND gate is F. d. F = Z Y X W , , , ) 14 , 12 , 5 , 4 , 3 , 1 , 0 ( G = Z Y X W , , , ) 14 , 13 , 12 , 9 ( /Y0 /Y1 /Y2 /Y3 /Y4 /Y5 /Y6 /Y7 A0 A1 A2 3-tm-8 Decmder G1 /G2 /Y0 /Y1 /Y2 /Y3 /Y4 /Y5 /Y6 /Y7 /G2 /m0 /m1 /m2 /m3 /m4 /m5 /m6 /m7 /m8 /m9 /m10 /m11 /m12 /m13 /m14 /m15 W W 0 1 X Y Z X Y Z /Y0 /Y1 /Y2 /Y3 /Y4 /Y5 /Y6 /Y7 /G2 /Y0 /Y1 /Y2 /Y3 /Y4 /Y5 /Y6 /Y7 /G2 /m0 /m1 /m2 /m3 /m4 /m5 /m6 /m7 /m8 /m9 W W 0 1 X Y Z X Y Z Implement F & G using 2 NAND gates but the same 4-to- 16 decoder (since they are functions of the same variables). To implement F: Link /m0, /m1, /m3,/ m4, /m5, /m12, and /m14 with a 7-input NAND gate, and the output of this NAND gate is F. To implement G: Link /m9 /m12, /m13, /m14 with a 4-input NAND gate, and the output of this NAND gate is G
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331 2. The truth table of the full adder is: X Y C in C out S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 The implementation is: I 0 I 1 I 2 I 3 S 1 S 0 Y S XY Cin Cin’ I 0 I 1 I 2 I 3 S 1 S 0 Y Cout 0 1
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332 3. The prime numbers are: 2, 3, 5, 7, 11, and 13. a. Link m2’, m3’, m5’, m7’, m11’, and m13’ with a 6-input NAND gate, and the output of this NAND gate is F. b. Link m0’, m1’, m4’, m6’, m8’, m9’, m10’, m12’, m14’, and m15’ with a 10-input AND gate, and the output of this AND gate is F. 4. Design a 1-bit comparator that takes in a bit X and a bit Y and outputs X<Y, X>Y, X=Y. Use a single 2-to-4 decoder and 1 single OR gate. /Y0 /Y1 /Y2 /Y3 /Y4 /Y5 /Y6 /Y7 A0 A1 A2 3-tm-8 Decmder G1 /G2 /Y0 /Y1 /Y2 /Y3 /Y4 /Y5 /Y6 /Y7 /G2 /m0 /m1 /m2 /m3 /m4 /m5 /m6 /m7 /m8 /m9 /m10 /m11 /m12 /m13 /m14 /m15 W W 0 1 X Y Z X Y Z Y0 Y1 Y2 Y3 A0 A1 2-to-4 Decoder X Y X<Y X>Y X=Y
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333 5. a. 2-to-4 decoder design b. 1-to-4 demux design S 0 D 0 D 1 D 2 D 3 D S 0 S 1 S 0 S 1 S 1 E B A Y 0 Y 1 Y 2 Y 3 0 X X 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 2-to-4 Decoder Y 0 E Y 1 Y 2 Y 3 A B B A B is the MSB Y 0 Y 1 Y 2 Y 3 E ABA B S 1 S 0 D 0 D 1 D 2 D 3 0 0 D 0 0 0 0 1 0 D 0 0 1 0 0 0 D 0 1 1 0 0 0 D
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334 6.
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This note was uploaded on 06/23/2008 for the course EE 101 taught by Professor Redekopp during the Fall '06 term at USC.

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AppendixAUnit8_3Sol - 8.3. Unit 3 Decoders, Encoder,...

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