AppendixAUnit8_4Sol

AppendixAUnit8_4Sol - 8.4. Unit 4 Bistables, Latches, and...

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347 8.4. Unit 4 – Bistables, Latches, and Flip-Flops 1. Examine the proposed bistable circuit below. Determine whether it is a valid bistable or not. If so, write out the function table, replacing the X and Y labels with the appropriate Set and Reset inputs. If it is not a valid bistable, indicate which operations (set, reset, remember) it cannot perform. This is a valid bistable because it can set, reset, and remember as shown in the table. We start by finding the hold case which is the input values that allow Q to feedback through the circuit. The hold case would be 1,1. From there we can activate one input at a time to find whether the output can be set and reset. X = S Y = R Q* 0 0 1 illegal 0 1 1 Set 1 0 0 Resest 1 1 Q Hold/Remember 2. Design a D-Latch using ONLY NAND gates (no inverters or any other gates.)
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This note was uploaded on 06/23/2008 for the course EE 101 taught by Professor Redekopp during the Fall '06 term at USC.

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AppendixAUnit8_4Sol - 8.4. Unit 4 Bistables, Latches, and...

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