AppendixAUnit8_6Sol

AppendixAUnit8_6Sol - 8.6. Unit 6 Datapath Design 1....

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359 8.6. Unit 6 – Datapath Design 1. Implement a circuit that takes in a 4-bit number X[3:0] and produces a 4-bit value Z[3:0] according to the following function: if X < 8 then Z = X + 10; else if X = 8 then Z = X – 3; else Z = X – 2; Using the building blocks below, implement this function WITHOUT ANY additional gates. Note: To subtract 3 and 2, take the 2’s complement. The 2’s comp. of 3 is 1101 and 2’s comp. of 2 is 1110. Also note that we can generate 1110 by passing 1101 and adding 1 using the Cin of the adder. O A<B O A>B O A=B 74LS85 A 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3 I A<B I A>B I A=B B3 B2 B1 B0 A3 A2 A1 A0 S0 S1 S2 S3 C0 C4 4-bit Binary Adder S G 1A 1Y 2Y 2-to-1 4-bit wide mux 2A 3A 4A 3Y 4Y 1B 2B 3B 4B X0 X1 X2 X3 0 0 0 1 1 0 0 X<8 X>8 0 0 1 0 1 1 0 1 1 X0 X1 X2 X3 Z0 Z1 Z2 Z3
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360 2. Design a circuit that takes in an 4-bit number X[3:0] and outputs a number Y, and performs the operation below. Assume these numbers are unsigned. Use 74LS85 comparators and 2-to-1 muxes. if(X >= 0111) Y = X else Y = 4X 4X would require 6 outputs and be X3 X2 X1 X0 0 0, thus even if we pass X we need to produce 6 outputs. O A<B O A>B O A=B 74LS85 A 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3 I A<B I A>B I A=B X0 X1 X2 X3 0 1 1 0 1 0 0 X >= 7 I 1 Y S I 0 I 1 Y S I 0 I 1 Y S I 0 I 1 Y S I 0 I 1 Y S I 0 I 1 Y S I 0 X0 X1 X2 X3 0 0 0 0 X0 X1 X2 X3 Y5 Y4 Y3 Y2 Y0 Y1
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361 3. Using (4) 74LS85 comparators and basic gates, design a circuit that takes in a 7-bit, unsigned number, X[6:0], and produces one output that checks: +27 < X < +101. X0 X1 X2 X3 1 1 0 1 1 0 0 X0 X1 X2 X3 1 0 1 0 1 0 0 O A<B O A>B O A=B 74LS85 A 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3 I A<B I A>B I A=B O A<B O A>B O A=B 74LS85 A 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3 I A<B I A>B I A=B O A<B O A>B O A=B 74LS85 A 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3 I A<B I A>B I A=B O A<B O A>B O A=B 74LS85 A 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3 I A<B I A>B I A=B X4 X5 X6 0 X4 X5 X6 0 1 0 0 0 0 1 1 0 X > 27 X < 101 27 < X < 101
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362 4. Design a circuit that takes in three 4-bit numbers: X[3:0], Y[3:0], and Z[3:0] and outputs three signals: MEDIAN_X, MEDIAN_Y, and MEDIAN_Z. Each of these outputs should only be ‘1’ when that input number is the median value. Thus if X=10, Y=3, Z=12 then MEDIAN_X should be ‘1’ and the other outputs should be ‘0’. If two or all three numbers are equal to the median value, each corresponding output should be asserted. If X=7,Y=7,Z=10, then MEDIAN_X and MEDIAN_Y should be asserted. Use 74LS85 comparators and basic logic gates. X0
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AppendixAUnit8_6Sol - 8.6. Unit 6 Datapath Design 1....

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