Department of Electrical and Computer Engineering
The University of Texas at Austin
EE 306, Spring 2008
Problem Set 2
Due: 18 February, before class
Ramesh Yerraballi, Instructor
TAs: Jasveen Kaur, Nady Obeid
Instructions:
This problem set should be your individual work. Please remember to put the name of the TA and the time for the
discussion section you would like the problem set turned back to you. Show your work.
(6pts)
(2.54, and from Problem Set 1)
Fill in the truth table for the equations given. The first line is done as an example. We have intentionally
left several blank output columns for you to use as you wish.
Q1 = NOT (NOT(X) OR (X AND Y AND Z))
Q2 = (NOT(X) OR NOT(Y) OR NOT(Z)) AND X
1.
(2.40)
(15pts, 3pts each part)
Write the decimal equivalents for these IEEE floating point numbers
0 10000000 00000000000000000000000
2
a.
1 10000011 00010000000000000000000
17
b.
0 01111100 01000000000000000000000
0.15625
c.
1 10000000 10010000000000000000000
3.125
d.
2.
This preview has intentionally blurred sections. Sign up to view the full version.
View Full Document0 11111111 00000000000000000000000
positive infinity
e.
(8pts)
(3.8)
(Please refer to the figure for problem 3.8 on page 85 of the book) The transistorlevel circuit below
implements the logic equation given below. Label the inputs to all the transistors.
Y = A AND (B OR C)
Y = NOT (A AND (B OR C))
3.
(5pts)
This is the end of the preview.
Sign up
to
access the rest of the document.
 Spring '08
 YERRABALLI
 Logic gate, Department of Electrical and Computer Engineering

Click to edit the document details