This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: ECE2022 A HOMEWORK # 4 D07
Name : 9 ECE Box Number: To make the grading easier, please draw a rectangle around each ﬁnal answer, where appropriate. Number your solutions just like below! This assignment is due Thursday,
April 12, bring to class. Problem 1 — 20 pts Attached to this homework you will ﬁnd speciﬁcation sheets for the DM74ALSOO Quadruple 2Input
NAND gate and the SN7442 4—Line to 10—Line Decoder. In the circuit we are designing, many 7442
inputs will have to connect to each 74ALSOO output and many 74ALSOO inputs will have to connect to each 7442 output. A major inﬂuence on our design will be exactly how many inputs can share
an output in each case. (a) Find and write down the following important values for the two chips: o DM74ALSOO 10H 2 43%  DM74ALSOO [CL = g m A o DM74ALSOO 11H = __7,_0AL______
 DM74ALSOO 1”: ml MA rm; MA  SN7442 10H 2 ~03 m4 1' *W MA.»  SN7442 10L 2 I6 «A  SN7442 11H 2 ‘10 A o SN7442 11L = — 3. 6 mA (b) Show the computation of the maximum number of 7442 gate inputs that can be driven High
from a single DM74ALSOO. r “OM/t u ,0
VOAA‘ (c) Show the computation of the maximum number of SN7442 gate inputs that can be driven Low from a single DM74ALSOO. U 3 "‘ ‘l .; lib—i .3 "lté M A
(d) What then is the maximum number of S 7442 gate inputs that can be reliably driven by single
DM74ALSOO? “rm 3 ,0, c? 1: 5 (e) Show the computation of the maximum number of D U 4ALSOO gate inputs that can be driven
High from a single SN7442. ‘i’Wa/tu = a 20 A
(f) Show the computation of the maximumzumber of DM74ALSOO gate inputs that can be driven Low fromasingle SN7442. L '6 m4 l _ [60 (g) What then is the maximum number of DM74AL «Agate inputs that can be reliably driven by Problem 2  25 pts '9.)
O N
0 Drain current [mA] _.
O __ Drain to source voltage [V] For the given MOSFET circuit and associated drain current characteristic and a threshold voltage
Of VTH = 1V,Z (a 5 pts) What is the intercept of the load line with the Drain to Source voltage (X) axis? (b 5 pts) What is the intercept of the load line with the Drain current (Y) axis?. 81/ \~ (c 10 pts) Fill our the following table. )6051' i: 0.2 v
V a LAT
fl
7
6
(d 5 pts) Plot VIM vs Vm using the values in your table. f
‘1
3
‘L O'zzvs‘é Collector Current Characten'stic git ( w) ib= 40M ib = 30 “A Problem 3 — 20 pts
For the given circuit and associated collector current characteristic: t chm 735 0'5?
((1) Also from the load line, estimate the minimum ib that will make the tians'mﬁfullyﬁsaa/mra d. K Lbﬁqﬂ 9% 375—” i IJAA Collector Current Characteristic 1.0 2.0 3.0 4.0 5.0
Vcc (V) Problem 4 — 20 pts For the given circuit, associated collector current characteristic and assuming Vbe = 0.7V (as is
typical for a forward biased baseemitter junction of a silicon transistor): (a) draw a load line. Vac, 1"! V 2.41/4 t it, ‘
(b) Determine the input current z'b.
(c) Estimate the collector current 2'6. ((1) Estimate the output voltage. l0 (\ __ _ i;
( \) lb 1:;sz —.. «:L— : 28 MA I;
(‘0 K 50“ g/ (L Q; I. gmA 4‘er (00...“sz ~ ..... wwwﬂ/ (A) m = lit—(imam thaw \v ...
View
Full
Document
This note was uploaded on 07/05/2008 for the course ECE 2022 taught by Professor Cyganski during the Spring '07 term at WPI.
 Spring '07
 Cyganski

Click to edit the document details