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Unformatted text preview: Name Sghé \‘L‘Qm S ECSE 2050 Analog Electronics Fall 2006 Final Exam Print your name on every page, show all work to ensure partial credit.
You must do problems 1, 2, 3, 4 Problem 1 ( 15 points)
Problem 2 (10 points)
Problem 3 (10 points)
Problem 4 (20 points) Solve 3 out of the next 5 problems. Clearly indicate which problems you do
not want graded by crossing out the numbers below. Problem 5 (15 points)
Problem 6 (15 points)
Problem 7 (15 points)
Problem 8 (15 points)
Problem 9 (15 points) Total Include units in answers where appropriate, or else
points will be deducted. ‘ Problem 1 (15 points) Name: $9 is. “you s The ﬁgure below shows a circuit for a digital to analog converter (DAC). The circuit
accepts a 4~bit input binary word (33823130), where a3,a2,a1,ao take the value of 0 or 1
(+5V), to provide an analog output V0 Vo L (a) Assume an ideal opamp, show that the output voltage V0 is given by V0 ——%[2000 +21a1+2202 +23%]
Where R1: is in KQ A .
lnuevkb Gum‘s... 349:" V6: V;
'  V [as on. :L + 0x“
1 ~ 4 Y4 “'6” + 2°“, 40% “85“1
A.
M 4 Q + 2 0‘: 'l' 9
:: 4’? Q3 4' a.
30V» 3
.—RF {QQOA’QO‘W" R
\6 (b) Find the value of RF such that V0 ranges from 0 to 12 volts. Va: 0 6. 0000 HH L (c) What is the output voltage for the digital word 1011) Us} #5 M l
Va: "" ‘9'8 23+ 3 +20] \é ,%3V in Problem 2 (10 points) For the logic gate shown below +5"I.IFr +5‘I.IFr +5"I.Ir Name: gem \YQU‘5 Assume VD and VBE = 0.7V, (a) Complete the following table
A B D1 D2 D3 D4 OUT
(ON/OFF) (ON/OFF) (ON/OFF) (ON/OFF)
O 0 o M o N 9F F P 0? F '5'
O 5 ON OVF 0?"; ON oCNc'Z)
5 0 sq: ON 0N OFF_ N9 ~7
5 5 o F F 0? F O N 0 N N 01
(\j (b) what is the function of the logic gate +
M
A + B NOR 3% e
(C) What is the base current in any of the two transistors when it is conducting?
"‘3 53: sum : “46.6)M
4 “w. 4 Name: Sago. Problem 3 (10 points) A 3—ingut CMOS NOR gate is required to achieve a delay of 150ps with a 0.1pF load
given the following information VDD =3.3V ' ’2' ~ [(0 5
C=O.lpF tr“ 7PM." PL” ' f
7p =150ps ._.. I§°
Vm = —VTP = 0.75V E O” = ZVFHL ! w, W 9'!
19:25—15? G [La [4 VelaVi» 3.. 1}»: 3 ~ in Km 4%
K!) =10—7
V =— “31.36 .51
w  ,L
L knew ( VDDJH“) (a) Draw the general schematic of the CMOS NOR Gate 5 872? W) :35WQn
‘9 ’39.“ u: (b) Size the Nchannel and Pchannel transistors in the 3input CMOS NOR gate to N satisfy the required delay time
Mﬂﬁgﬂl
mg a: ‘3 ﬁlth
V‘ q CL
3 Y 3 9 ‘1 " ‘°.._.....—.° Name: Choose 3 out of the following 5 guestions Problem 5 (15 points) +V Given: Vd = Vil  Viz ch =(Vi1 + Vi2)/2
V0ut(d):VO 1 'VOZ
Vout(cm)=(Vol+V02)/2 The transistors have [30 = 160 W2 W1 mm A‘  5 milk ﬁe £0.6wn. \( f. ' .. [5°7‘zg'v
G" ‘52" “37:77
U. 26.6ik5”
 5L
x’w: b) Draw the differential mode V2 circuit model and determine the differential voltage
gain: Avdzvout(d)/Vd'
S \L VO‘ N '— VA (Tr + ('+F) (loo) VH
LV _QO’ (3 \HV “3 Jaub//Oi2k / vent A} c) What is the differential mode input resistance for this circuit?)
S Rial?! air“ + (HP to 8 (h d) Determine the single sided common mode gain using V01 as the output. It.
bsﬂ {Vo‘ took ’5 e) What is the CMRR in dB for this circuit if a single sided output is used? 40.3 \.. 463358 ’V out Problem 6 (15 points) Name;
0 HEY
5k
R1
C3 Vout
Cl .
RS 50k Q1 luF Rload
Vs i UluF 5k
r3 \,
Keri/J R?
QDUF 1k
02 The circuit above has an N channel enhancement type MOSFET with K’\l\//l;—:2mA/V2
and VFZV. R1 and R2 are such that IDQ=1.5mA and R1//R2=200k£2. ’V
a) Calculate the mid freqiiincy voltage gain, Avm(total)=Vout/V s.
\IQJ “5m (SM/5K) x R‘// [32, W :
VS a/Muks $3
3:»: 3k‘%lp:l2xzmn.s;¢ Qﬂfmft/V
VGWF rk y J '4. ’ ?
’V’S'" : "' 9.5 3.36” b) Given that Cgs=5pF and ng=2pF, draw the small signal model appropriate for
high frequency analysis and estimate fh, which is the high frequency 3d]; point. (3Q Problem 7 (15 points) Namezw 25:1 \(x D1 D Vout \I‘ : gs ’ ‘20
120v —v .  .—
(rms Rload 7' v”
200H
2 0.2k Vx : 43
. v 632? Assume the diode in the circuit shown has a forward voltage drop of 0.7V but otherwise
is ideal. The transformer is ideal. Note that the input frequency is 200Hz. a) Sketch the waveform for Vout as a function of time. Cover at least one full cycle of
Vs. Determine the peak voltage and label it on the sketch. Label the time axis. MémEtOI’Qﬁd 43mg =45,o' ll Problem 7 continued Name: b) A 400uF capacitor is added in parallel to Rload. Sketch the waveform for Vout with
the capacitor added. Determine and label the peak voltage, minimum voltage and the voltage ripple, and label the time axis. _  1
Mercatargrid ~yaﬁtude =45.o" model the diode as having a forward drop of 0.6V and an effective series 0) For this part,
resistance of 100. Determine the peak value of the output voltage for this model for the “3 51 V
circuit without the capacitor. 1‘ ‘ VJ» o o
:— VS
20 o w 200
*‘v D '30 0 to o D :(6. 0‘5 t,»
Z! 0 12 Name: Problem 8 (15 pOintS) The PNP BIT if; {he circuit belcw hm; B1: = 50. Finﬁ the value of the cm‘rents; and V’Ol’fa‘iﬁ
indicated an the schematic diagram. Vcltage values are Wiih respect to gl‘ound potentiaL 0.? V 10V 13 ECSE~2050
Analog Electron Problem 18.2 The PNP BIT in the circuit below has indicated on the s ics chematic diagram. V0 Spring 2006 £3; = 58. Find the mine of the currents and vokages
Rage values are with impact to grmmd potential. Name:
Problem 5X1 Spts) The diode circuit shown below has the following input waveform a)Plot Vo on the axes below for the case when the diodes are ideal. Label important
voltages on your plot v; = ~5v 0* 91' Db OFF
V02: L1" Di “:5 1/ ‘
V’: = 5v {3, 132 95 O N
101ml oraclé vow—=0 10 b)Plot Vo on the axes below for the case when the piecewise linear model with Vpo=0.65
and r9 =50 Ohm is used for the diodes. Label imperial]: voltages on your plot. 5415x1365)
,Hc +150 V."'~=‘SV {a . '3‘ 2. 65m Va ’3: Uf~ {le :z_2\55v '1‘; c)For the same input signal but using the Zener diode circuit shown below, plot V0 and
label important voltages on your plot N W ll ...
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This note was uploaded on 07/05/2008 for the course ECSE 2050 taught by Professor Monahella during the Spring '08 term at Rensselaer Polytechnic Institute.
 Spring '08
 MonaHella

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