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ie_sp07_lecture22_dig2

# ie_sp07_lecture22_dig2 - Lecture 22 Digital Electronics_2 1...

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1 Lecture 22 Digital Electronics_2

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2 Chapter Goals Analysis of saturated load inverters Static and Dynamic Response Introduce CMOS logic concepts Explore the voltage transfer characteristics CMOS inverters Learn to design basic CMOS logic gates Discuss static power in CMOS logic Present noise margins for CMOS logic
3 NMOS Inverter with a Resistive Load The resistor R is used to “pull” the output high • M S is the switching transistor The size of R and the W/L ratio of M S are the design factors that need to be chosen

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4 Load Line Visualization The following illustrates the operation of the NMOS output (v DS ) characteristics where the following equation describes the load line R i V v D DD DS - =
5 NMOS with Resistive Load Design Example Design a NMOS resistive load inverter for – V DD = 3.3 V P = 0.1 mW when V L = 0.2 V – K n = 60 μ A/V 2 – V TN = 0.75 V Find the value of the load resistor R and the W/L ratio of the switching transistor M S

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6 Example continued First the value of the current through the resistor must be determined by using the following: The value of the resistor can now be found by the following which assumes that the transistor is on or the output is low: A V mW V P I DD DD μ 3 . 30 3 . 3 1 . 0 = = = = - = - = k A V V I V V R DD L DD 102 3 . 30 2 . 0 3 . 3 μ
7 Example Continued For v I = V L = 0.2V, the transistor’s v GS will be less than the threshold voltage, therefore it will be operating in the triode region. Using the linear equation for a MOSFET, the W/L ratio can be found: ( 29 1 1 1 03 . 1 2 . 0 2 2 . 0 75 . 0 3 . 3 10 60 3 . 30 2 6 ' 2245 = - - × = - - = - S S L L TN H S n D L W L W A V V V V L W K I μ

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8 On-Resistance of M S The NMOS resistive load inverter can be thought of as a resistive divider when the output is low, described by the following expression: R R R V V on on DD L + =
9 On-Resistance of M S (cont.) - - = = 2 1 ' DS TN GS n D DS on v V v L W K i v R

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