ie_sp07_lecture23_dig3_1

# ie_sp07_lecture23_dig3_1 - 1 Lecture 23 Digital...

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Unformatted text preview: 1 Lecture 23 Digital Electronics_3 2 Chapter Goals • Static and Dynamic Response • Introduce CMOS logic concepts • Explore the voltage transfer characteristics CMOS inverters • Learn to design basic CMOS logic gates • Discuss static power in CMOS logic • Present noise margins for CMOS logic 3 Static Power Dissipation • Static Power Dissipation is the average power dissipation of a logic gate when the output is in both the high and low states • I DDH = current in the circuit for v O = V H • I DDL = current in the circuit for v O = V L • Since I DDH = 0 A for v O = V H : 2 DDL DD DDH DD av I V I V P + = 2 DDL DD av I V P = 4 Dynamic Power Dissipation • Dynamic Power Dissipation is the power dissipated during the process of charging and discharging the load capacitance connected to the logic gate Discharging Charging 5 Dynamic Power Dissipation • Based on the energy equation, the energy delivered to the capacitor can be found by: • The energy stored by the capacitor is: • The energy lost in the resistive elements is given by: 2 ) ( ) ( ) ( ) ( DD V V C DD DD D CV dv t i V C dt t i V E C C = = = ∫ ∫ ∞ ∞ 2 2 DD D CV E = 2 2 DD S D L CV E E E =- = 6 Dynamic Power Dissipation • The total energy lost in the first charging and discharging of the capacitor through resistive elements is given by: • Thus it can be seen that for every cycle (frequency) that the gate is changed, the dynamic power dissipation is given by: 2 2 2 2 2 DD DD DD TD CV CV CV E = + = f CV P DD D 2 = 7 Dynamic Behavior Capacitance in MOS Logic Circuits • The MOS device has the capacitances C SB , C GS , C DB , and C GD that need to be considered for dynamic response analysis, but depending on the configuration, some of them will be shorted out as seen in the first figure • The capacitance seen at a node can be lumped together as seen in the second figure 8 Fan-out Limitations • Static design constraints are not usually important for MOS logic circuits since they normally drive capacitive loads (i.e. the gate of a MOS) • As the number of gates the output (fan-out) of a logic device has to drive, the load capacitance increases, and the time response decreases...
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ie_sp07_lecture23_dig3_1 - 1 Lecture 23 Digital...

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