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HW 11 Solutions - Carnegie Mellen University Department...

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Unformatted text preview: Carnegie Mellen University Department ei‘ Electrical and Cempnter Engineering Iii-11H]: Intretluctien te Electrical and Cementer Engineering Spring 1111]? Prehleni Set #11 [Last flnei) Due: Friday, May 4 at 4:111] pm. i Name g E! [U {h it)“; - Sectien Fer this emblem set. yea are te illl In year answers directly en these sheets and turn this entire set In by 1113!] PM I'll] Friday, May ‘I. There will lie I place far each sectinn nulaitle nf my nffice at EH 1110?. Na late linme'wnrk papers will he accepted. The ilnal exam will he given en Menday, May 14 Heat 5:311 — 11:31] PM in 11112315. The final rah-at eernpefitien trill teite place an Wednesday. May 9 [Reading [lay] starting at I] AM. Reese TBA. Pizza will IJE served at nn-nn. All in the class are welcnme, regardless nf whether year team centpetes tn the final eeinpetitien er net. Came cheer en year classmates! Please STaPLE year pages together prier te taming year set in. thkm 1: Csnsidsr the fmlswing state transition ishls. The external input is th-s finite state msshins is "K“. and 1hr.- sslsmsl sulput is '"s'". Fill in the fullswing stsmtrsnsitisn dismsm fuss this digissl system. ‘t'su slmuld lsth wuss mansilisn an-aws as m {"input .16; value'T'oulput ‘s" vslus") as we: did in class. KL Problem I: In this prnhlsm gnu will design a binary nnuntsr that EDLIIIIE in hiflflT‘f fi‘nm I'wn {El-11]} tn six [I It)“; and repeats itsnlf indefinitely. Is} Fill in thrs following stntn tmnsitinn table below far this system {the unusntt slates are “dnn’t earn" slatns}: t I] (11+ Q2+ III I II E Ill IIIHHIIH HHHIEIII‘g {1:} Fill in ms fullnwing [ii-maps far the nest stale Inputs. HE. D] . and D0. “fit—man iLlfllfl 5 In} Draw the circuit schematic using punitive eflge-uiggemfl D Flip-rflflpfi. Tau may use Dilly t'I't'IJ-ittpllt AND, GR. HAND. and HIDE. gates, and inverters. Theta D flip-flaps have set and reset inputs that are asserted HIGH {positive assertion}. Add to yen: circuit a line labeled START, such that when STaRT is asserted HIGH. the System will 3e immediately tn the initial state. which is state em. Pirahlam 3: In this prabiam yau will design a finite state machine that afilca fltraagh the fallawiag air-t atataa and repeats itself: IlfllllI IE1] HUI lL'Ill 1H] flflfl {a} F1“ in the fallflwittg atatl: transitimt tab]: bulaw far this ayatcm (flu: unuaad status an: “don't can" amass}: D1 = D1 = [ID = {11+ (11+ (10+ T {1:} Fill in the fullmuing K‘maps fur the next state inputm D1. D], and DL'I- B {:1 Draw the circuit using negative edge-triggered D F iipflcps. "r'cu may use ml},r two-input AND Eaten; twnuinput DR gates, and inverters. Mae. thee: D flip-flcpe have set and. reset inputs that are asscflctl LEW [negative nasal-Linn}. Add tc: your circuit a lime lahclct] START, such that when START is EH-Scflcd LBW, I11: system 1will gc iIflmfliifiIElijf tt} the initial state, which is stat: 104]. a. EV fl. 1 ‘ '1. m .1 “L “1 fli ’ h' 3 El“ Q: ' Problem 4; Below is a state-militia diagram which implcmmts a digital 33mm. “fan are In dflign the circuit which pfirfflnttfl tilt: sequcnce DfEt-‘EIIE outlined in this diagram. There is one input {I} tt: this 53mm]. and an: flutpttt. ”I“. If] START I I \ 0 ’3 It'll] in} Fiil in the: slut: transitinn tab]: hcluw fur th: state transition diagram ahmre. PRESENT GUI'PUT STATE i] 1 fl 1 1D {1:} Fill In the fullnwing Iii-maps for I11: next shite inputa, D1 and D1], and the output ‘5’. H {e} Draw the eireuit schematic which implements. the expressieus yen derived frem the it-n'tepts in part {h}. Use pesitive edge-triggered fliprflflph in yew isnplemeetetten. The set and teeet lines are asserted HJGH fer these flip-flees. Add te “yew circuit e line labeled START, such that when START is esSerted HIGH. the system will an hemedistety te the initial state. whieh is state fll. “fee may use any tnre- lnpttt gates that yen like fer realizing yen: expressiens {AMI}. DE HAND, MGR, KER, KNEE]- Be sure It: Clearly merit: yum input "I", eutpnt "Hi". eIe-elt {ELK}, and START line. XE it ~—-r ‘Insw’r ...
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