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Unformatted text preview: Carnegie Mellen University
Department ei‘ Electrical and Cempnter Engineering Iii11H]: Intretluctien te Electrical and Cementer Engineering Spring 1111]? Prehleni Set #11 [Last ﬂnei)
Due: Friday, May 4 at 4:111] pm. i
Name g E! [U {h it)“;  Sectien Fer this emblem set. yea are te illl In year answers directly en these sheets and turn this entire set
In by 1113!] PM I'll] Friday, May ‘I. There will lie I place far each sectinn nulaitle nf my nfﬁce at EH
1110?. Na late linme'wnrk papers will he accepted. The ilnal exam will he given en Menday, May 14 Heat 5:311 — 11:31] PM in 11112315. The final rahat eernpeﬁtien trill teite place an Wednesday. May 9 [Reading [lay] starting at I]
AM. Reese TBA. Pizza will IJE served at nnnn. All in the class are welcnme, regardless nf whether year team centpetes tn the ﬁnal eeinpetitien er net. Came cheer en year classmates! Please STaPLE year pages together prier te taming year set in. thkm 1: Csnsidsr the fmlswing state transition ishls. The external input is ths ﬁnite state msshins is "K“. and
1hr. sslsmsl sulput is '"s'". Fill in the fullswing stsmtrsnsitisn dismsm fuss this digissl system. ‘t'su slmuld lsth wuss mansilisn
anaws as m {"input .16; value'T'oulput ‘s" vslus") as we: did in class. KL Problem I:
In this prnhlsm gnu will design a binary nnuntsr that EDLIIIIE in hiﬂﬂT‘f ﬁ‘nm I'wn {El11]} tn six [I It)“; and
repeats itsnlf indeﬁnitely. Is} Fill in thrs following stntn tmnsitinn table below far this system {the unusntt slates are “dnn’t earn"
slatns}: t I]
(11+ Q2+
III
I
II
E
Ill IIIHHIIH
HHHIEIII‘g {1:} Fill in ms fullnwing [iimaps far the nest stale Inputs. HE. D] . and D0. “ﬁt—man iLlﬂlﬂ 5 In} Draw the circuit schematic using punitive eﬂgeuiggemﬂ D Fliprﬂﬂpﬁ. Tau may use Dilly t'I't'IJittpllt
AND, GR. HAND. and HIDE. gates, and inverters. Theta D ﬂipflaps have set and reset inputs that are
asserted HIGH {positive assertion}. Add to yen: circuit a line labeled START, such that when STaRT
is asserted HIGH. the System will 3e immediately tn the initial state. which is state em. Pirahlam 3: In this prabiam yau will design a ﬁnite state machine that aﬁlca ﬂtraagh the fallawiag airt atataa and
repeats itself: IlﬂlllI
IE1]
HUI
lL'Ill
1H]
ﬂﬂﬂ {a} F1“ in the fallﬂwittg atatl: transitimt tab]: bulaw far this ayatcm (ﬂu: unuaad status an: “don't can"
amass}: D1 = D1 = [ID =
{11+ (11+ (10+ T
{1:} Fill in the fullmuing K‘maps fur the next state inputm D1. D], and DL'I B {:1 Draw the circuit using negative edgetriggered D F iipﬂcps. "r'cu may use ml},r twoinput AND
Eaten; twnuinput DR gates, and inverters. Mae. thee: D ﬂipﬂcpe have set and. reset inputs that are
asscﬂctl LEW [negative nasalLinn}. Add tc: your circuit a lime lahclct] START, such that when START
is EHScﬂcd LBW, I11: system 1will gc iIﬂmﬂiiﬁIElijf tt} the initial state, which is stat: 104]. a. EV
ﬂ. 1 ‘
'1.
m .1 “L “1
ﬂi ’ h' 3 El“
Q: ' Problem 4; Below is a statemilitia diagram which implcmmts a digital 33mm. “fan are In dﬂign the circuit
which pﬁrfﬂnttﬂ tilt: sequcnce DfEt‘EIIE outlined in this diagram. There is one input {I} tt: this 53mm].
and an: ﬂutpttt. ”I“. If] START I I \
0 ’3 It'll] in} Fiil in the: slut: transitinn tab]: hcluw fur th: state transition diagram ahmre. PRESENT GUI'PUT
STATE i]
1
ﬂ
1 1D {1:} Fill In the fullnwing Iiimaps for I11: next shite inputa, D1 and D1], and the output ‘5’. H {e} Draw the eireuit schematic which implements. the expressieus yen derived frem the itn'tepts in part
{h}. Use pesitive edgetriggered fliprﬂﬂph in yew isnplemeetetten. The set and teeet lines are asserted
HJGH fer these ﬂipﬂees. Add te “yew circuit e line labeled START, such that when START is esSerted
HIGH. the system will an hemedistety te the initial state. whieh is state ﬂl. “fee may use any tnre
lnpttt gates that yen like fer realizing yen: expressiens {AMI}. DE HAND, MGR, KER, KNEE] Be
sure It: Clearly merit: yum input "I", eutpnt "Hi". eIeelt {ELK}, and START line. XE it ~—r ‘Insw’r ...
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 Fall '07
 Williams

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