CA Project - COMPUTER ARCHITECTURE CS556AH2 INSTRUCTION SET...

Info icon This preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
COMPUTER ARCHITECTURE CS556AH2 INSTRUCTION SET ARCHITECTURE FOR MICROPROCESSOR Project Report Submitted by Mahender Kasarla Saketh Karanam Naveen Kumar Matta 08.03.2015
Image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Overview 16 bit memory words, instructions, and general purpose registers. • Opcodes are 5 bits (fixed length) and 11 bits for operands. • Where memory is word addressable. • All arithmetic is 16 bit integer. • Here 3 bit conditional flag. The flag is set by cmp and by the arithmetic operations. Flag bits are read by the conditional jump operations in the instruction set. • Instructions use immediate, direct, register, and register indirect addressing. • The system uses a load store architecture only the load and store operations access memory •The system uses register indirect rather than indirect addressing, this way we can’t use indirect operations to read memory to find the jump target. Graphical Representation of Words stored in Memory
Image of page 2
REGISTERS: We know Register are used to accept, store, and transfer data, instructions that are being used immediately by the System. The ISA has eight general purpose programmable registers numbered 0 to 7 the assembly code use the octal value (or decimal) when referencing the register. We don’t need special prefix (e.g. r5). Like r0= 000, r1=001, r2=010, r3=011, r4=100, r5=101, r6=110, r7=111 Registers Operations:- Instruction fetch (IF) Here the instruction pointed to by the PC is fetched from memory into the instruction register of the CPU, and the PC is incremented and point to the next instruction in the memory. Instruction decode/register fetch (ID) The instruction is decoded, ALU input registers get the operands transferred from the registers in the second half of the stage. Execution/effective address calculation (EXE) The ALU operates on the operands from ALU input registers and eventually puts the result into ALU output register. The contents of this register depend on the type of instruction which we use. If the instruction is: Register to register (e.g. arithmetic/logical): the ALU outputs the results of the operations into the ALU output registers; memory reference (e.g. load/store): all ALU output registers contain an effective memory address;
Image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Control transfer (e.g. branch on equal), then the ALU produces the jump / branch target address (which is stored in the ALU output register) and, at the same time, the branch direction.
Image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern