lect-week6-dctran-fall2016(1)

lect-week6-dctran-fall2016(1) - DC Transient Response DC...

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DC & Transient Response 1 DC and Transient Response
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CMOS VLSI Design CMOS VLSI Design 4th Ed. DC and Transient Response 2 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation
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CMOS VLSI Design CMOS VLSI Design 4th Ed. DC and Transient Response 3 Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing V DD V g = V DD If V s > V DD -V t , V gs < V t Hence transistor would turn itself off nMOS pass transistors pull no higher than V DD -V tn Called a degraded “1” Approach degraded value slowly (low I ds ) pMOS pass transistors pull no lower than V tp Transmission gates are needed to pass both 0 and 1 V DD V DD
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CMOS VLSI Design CMOS VLSI Design 4th Ed. DC and Transient Response 4 Pass Transistor Ckts
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CMOS VLSI Design CMOS VLSI Design 4th Ed. DC and Transient Response 5 DC Response DC Response: V out vs. V in for a gate Ex: Inverter When V in = 0 -> V out = V DD When V in = V DD -> V out = 0 In between, V out depends on transistor size and current By KCL, must settle such that I dsn = |I dsp | I dsn I dsp V out V DD V in
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CMOS VLSI Design CMOS VLSI Design 4th Ed. DC and Transient Response 6 Transistor Operation Current depends on region of transistor behavior For what V in and V out are nMOS and pMOS in Cutoff? Linear? Saturation?
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CMOS VLSI Design CMOS VLSI Design 4th Ed. DC and Transient Response 7 nMOS Operation Cutoff Linear Saturated V gsn < V tn V in < V tn V gsn > V tn V in > V tn V dsn < V gsn – V tn V out < V in - V tn V gsn > V tn V in > V tn V dsn > V gsn – V tn V out > V in - V tn I dsn I dsp V out V DD V in V gsn = V in V dsn = V out
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CMOS VLSI Design CMOS VLSI Design 4th Ed. DC and Transient Response 8 pMOS Operation Cutoff Linear Saturated V gsp > V tp V in > V DD + V tp V gsp < V tp V in < V DD + V tp V dsp > V gsp – V tp V out > V in - V tp V gsp < V tp V in < V DD + V tp V dsp < V gsp – V tp V out < V in - V tp I dsn I dsp V out V DD V in V gsp = V in - V DD V dsp = V out - V DD V tp < 0
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CMOS VLSI Design CMOS VLSI Design 4th Ed.
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