Title: Recent Advances in Silicon and Non-Silicon Nanoelectronic Devices for High-Performance, Energy Efficient Logic Applications Abstract Description: Sustaining Moore's Law of doubling CMOS transistor density every twenty four months will require not only shrinking the transistor dimensions, but also introduction of new materials and novel device architectures to reduce energy consumption. The physical gate length of Si MOS transistors used in today's 65nm logic technology node is about 35nm, and it is projected that the size of transistors will reach about 10-15nm in 2011. Through silicon innovations such as strained-Si channels, high-K dielectric/metal-gate stacks, and the non-planar multiple gate "Tri-gate" transistor architecture, CMOS transistor scaling and Moore's Law will continue at least through the middle of next decade. Beyond that, in the limits of nanometer scale, the dominant practical constraints arise from power dissipation in ever smaller volumes, making
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