04codegen - 1 CSE 450: Compilers K. Stirewalt Code...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 1 CSE 450: Compilers K. Stirewalt Code generation Topics: Target machine code Instruction selection Readings: Dragon Book 8.1 - 8.3 CSE 450: Compilers K. Stirewalt Project 5 Q&A Questions??? CSE 450: Compilers K. Stirewalt Structure of a Compiler Source Language Target Language Semantic Analyzer Syntax Analyzer Lexical Analyzer Front End Code Optimizer Target Code Generator Back End Int. Code Generator Intermediate Code CSE 450: Compilers K. Stirewalt Today Source Language Lexical Analyzer Front End Code Optimizer Target Code Generator Back End Int. Code Generator Intermediate Code CSE 450: Compilers K. Stirewalt Issues in design of target code generator Input to the code generator High-level or low-level IR? Target language Assembly code, virtual machine code Instruction selection Register allocation Evaluation order CSE 450: Compilers K. Stirewalt Issues in design of target code generator Input to the code generator High-level or low-level IR? Target language Assembly code, virtual machine code Instruction selection Register allocation Evaluation order 2 CSE 450: Compilers K. Stirewalt Generating assembly code from three-address IR Three-address code is a low-level IR Close to assembly language But not contains features that are not directly implementable in an assembly lang Examples: Names in IR must be converted to addresses in the target code Some instructions (e.g., param, call, etc) lead to a sequence of target instructions Data representation issues must be addressed CSE 450: Compilers K. Stirewalt Target language RISC-like machine: 16 general purpose registers r0 - r15 Each can hold one machine word (4 bytes) A stack pointer register (SP) Project #6 will use a variant of this machine, with an additional base- pointer (BP) register CSE 450: Compilers K. Stirewalt Categories of instructions Load operations Store operations Computation operations Unconditional jumps Conditional jumps CSE 450: Compilers K. Stirewalt Load instruction General form: LD dst, addr Loads the value in location addr into register dst Here, addr could be a register, a memory location, or a constant If memory location, can be computed using various addressing modes Denotes the assignment dst = addr CSE 450: Compilers K. Stirewalt Addressing modes Immediate addressing: Address = constant literal E.g: LD R0, #50 moves the literal 50 into R0 Memory addressing: Address = name x referring to the memory location reserved for x Name interpreted as l-value of x E.g: LD R0, emplID where emplID names a location in memory...
View Full Document

Page1 / 6

04codegen - 1 CSE 450: Compilers K. Stirewalt Code...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online