Cheat Sheet For 118 Final

Cheat Sheet For 118 Final - In Domino Logic Put nMOS gates...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
When finding the 10% to 90% rise time t r for a circuit given a certain capacitance and ‘on resistance’. Use this formula to calculate t r : r V V F DD V V F DD F t t F F DD F F DD t V V RC V V dV RC dt dV V V RC dt dt dV C R V V i DD DD DD DD = - - = - = - = = - = 9 . 0 1 . 0 9 . 0 1 . 0 ) ln( % 90 % 10 Reading -The content of the memory is a 1 , stored at Q. -The read cycle is started by precharging both the bit lines to a logical 1 , then asserting the word line WL, enabling both the access transistors. -The second step occurs when the values stored in Q and Q are transferred to the bit lines by leaving BL at its precharged value and discharging BL through M 1 and M 5 to a logical 0 . -On the BL side, the transistors M 4 and M 6 pull the bit line toward V DD , a logical 1. -If the content of the memory was a 0 , the opposite would happen and BL would be pulled toward 1 and BL toward 0 . Writing Apply the value to be written to the bit lines. -If we wish to write a
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 07/25/2008 for the course EEC 118 taught by Professor Raj during the Spring '08 term at UC Davis.

Page1 / 2

Cheat Sheet For 118 Final - In Domino Logic Put nMOS gates...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online