D2XL_to_DIo1 - GND A40 VU B2 VU DIO1B Pin Signal D2XL Pin...

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Digilab Board Interconnect Table Digilent, Inc. Copyright Digilent, Inc. All Rights Reserved Document: 510-006 Digilab Digital I/O 1, Rev B to Digilab D2XL DIO1B Pin Signal D2XL Pin Signal FPGA Pin A1 B39 B39 88 A2 B40 B40 18 A3 B37 B37 64 A4 B38 B38 42 A5 B35 B35 3 A6 B36 B36 76 A7 B33 B33 5 A8 B34 B34 4 A9 B31 B31 7 A10 B32 B32 6 A11 B29 B29 11 A12 B30 B30 10 A13 B27 B27 13 A14 B28 B28 12 A15 B25 B25 20 A16 B26 B26 19 A17 B23 B23 22 A18 B24 B24 21 A19 B21 B21 26 A20 B22 B22 23 A21 B19 B19 28 A22 B20 B20 27 A23 B17 B17 30 A24 B18 B18 29 A25 B15 B15 40 A26 B16 B16 31 A27 B13 B13 43 A28 B14 B14 41 A29 B11 B11 46 A30 B12 B12 44 A31 BLU B9 B9 48 A32 PS2D B10 B10 47 A33 GRN B7 B7 50 A34 PS2C B8 B8 49 A35 RED B5 B5 54 A36 HS B6 B6 51 A37 VCC B3 VCC A38 VS B4 B4 56 A39 GND B1
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Unformatted text preview: GND A40 VU B2 VU DIO1B Pin Signal D2XL Pin Signal FPGA Pin B1 CA A39 A39 58 B2 SW1 A40 A40 57 B3 CB A37 A37 60 B4 SW2 A38 A38 59 B5 CC A35 A35 63 B6 SW3 A36 A36 62 B7 CD A33 A33 66 B8 SW4 A34 A34 65 B9 CE A31 A31 74 B10 SW5 A32 A32 67 B11 CF A29 A29 77 B12 SW6 A30 A30 75 B13 CG A27 A27 79 B14 SW7 A28 A28 78 B15 DP A25 A25 83 B16 SW8 A26 A26 80 B17 BTN2 A23 A23 85 B18 BTN1 A24 A24 84 B19 BTN4 A21 A21 87 B20 BTN3 A22 A22 86 B21 A1 A19 A19 94 B22 LD1 A20 A20 93 B23 A2 A17 A17 96 B24 LD2 A18 A18 95 B25 A3 A15 A15 100 B26 LD3 A16 A16 99 B27 A4 A13 A13 103 B28 LD4 A14 A14 102 B29 A11 A11 113 B30 LD5 A12 A12 112 B31 A9 A9 115 B32 LD6 A10 A10 114 B33 A7 A7 118 B34 LD7 A8 A8 117 B35 BTN5 A5 A5 121 B36 LD8 A6 A6 120 B37 VCC A3 VCC B38 LDG A4 A4 122 B39 GND A1 GND B40 VU A2 VU...
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This note was uploaded on 07/25/2008 for the course PHY 440 taught by Professor Abolins during the Spring '06 term at Michigan State University.

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