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Unformatted text preview: Programmable Logic Design – I Introduction In labs 11 and 12 you built simple logic circuits on breadboards using TTL logic circuits on 7400 series chips. This process is simple and easy for small circuits. With increasing complexity of the logic circuitry the possibility of wiring errors grows and it becomes increasingly difficult to debug the circuit. Another problem is the difficulty in finding all the needed logic circuitry on available chips. To address these problems the electronics industry has developed the concepts of Programmable Logic Devices (PLD’s) or Field Programmable Logic Devices (FPGA’s). The basic idea behind these devices is the notion that logic circuitry of arbitrary complexity can be constructed from simple gates connected with appropriate links and the technical advance that has made this possible is the development of large gate arrays with computer programmable links. The design process then consists of specifying the logic design by means of a logic design language such as VHDL or by entering it on a schematic layout. A computer program then turns this design into a series of instructions that are downloaded into the chip to establish the desired logic circuitry. Facilities are provided to specify the pin out of the logic, to control placement of logic circuits on the chip and to impose timing constraints. Our last two experiments can be considered as one long experiment that will be graded when both of them are finished. Thus you should not feel an urgency to finish everything in the first write-up, as you will have a chance to catch up later. Design Tools For our designs we will be using the Xilinx Corporation (www.xilinx.com) ISE Foundation 6.1i package along with the ModelSim Xilinx Edition II HDL simulation software. For reasons of lack of time we will restrict ourselves to Schematic Entry for our circuit description although the software supports a number of high level languages such as VHDL. We will sample only a few of the features and capabilities of this software package which is widely used in the electronics industry today. Hardware We will download our designs into a Digilab D2XL board connected to a Digilab Digital I/O board (DI01) shown in Figure 1 below. The FPGA chip on the D2XL board is a member of the Spartan II family, the XC2S30, embodying 972 logic cells with a total of 30,000 gates. While this size of device was state-of-the-art a few of years ago, rapid advances in technology have pushed the largest device sizes to many millions of gates. The D2XL board’s I/O resources are limited to a single pushbutton and LED for use with a test program to verify proper operation. A large variety of I/O devices, however, are available on the DI01 board attached to theD2XL by means of two 40 pin connectors. Our two experiments will exploit the features of the D2XL/DI01 combination to design a number of circuits that will demonstrate the usefulness of this procedure. to design a number of circuits that will demonstrate the usefulness of this procedure....
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This note was uploaded on 07/25/2008 for the course PHY 440 taught by Professor Abolins during the Spring '06 term at Michigan State University.
- Spring '06