L05 lecture

L05 lecture - Bias Current Sources Applications Design...

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EECS 240 Lecture 5: Biasing © 2004 B. Boser 1 Bias Current Sources Applications Design objectives Output resistance (& capacitance) Voltage range (V min ) – Accuracy – Noise Cascoding High-Swing Biasing EECS 240 Lecture 5: Biasing © 2004 B. Boser 2 Current Mirror Bias Noise Cascoding

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EECS 240 Lecture 5: Biasing © 2004 B. Boser 3 Noise M2 (and I ref !) can add noise Choose small M (power penalty), or Filter at gate of M1 Current source FOMs Output resistance R o Noise resistance R N Active sources boost R o , not R N ( ) ( ) o o v o m N N B m B m m B d d on r R M a r M g R f R T k f M g T k f g M g T k i M i i = << + = + = = + = + = + = 1 1 1 1 4 1 4 4 1 0 1 1 1 2 2 1 2 2 2 2 1 2 γ γ γ γ EECS 240 Lecture 5: Biasing © 2004 B. Boser 4 V min versus Noise M KI V M g R k V k V D m N + = + = = × = 1 2 1 1 2 ... 1 typ. * 1 min 1 1 min γ γ Voltage required for large Ro (saturation): V min ~ V* (based on intuition from square-law model) Minimizing noise (for given I D ): Æ large R N Æ large V min (k >> 1) At odds with signal swing (to maximize the dynamic range)
EECS 240 Lecture 5: Biasing © 2004 B. Boser 5 Bipolar’s, GaAs, … BJT and R E contribute noise Increasing R E lowers overall noise BJT and MOS exhibit essentially same noise / V min tradeoff Lowest possible noise source is a resistor (and large V min , V DD ) Q1 Q2 R E R E i o I ref C big f R g R g i R g i i E m E m Rn E m cn on + + + = 4 4 3 4 4 2 1 4 43 4 42 1 E R 2 2 BJT 2 2 2 1 1 1 0 a) = E m R g 1 b) >> E m R g f Tg k i m B on = 2 2 f R T k i E B on = 1 4 2 C C t m N I I V g R by set 2 2 = = min min min V V V I V R R sat ce C E N = = K I V R D MOS N 2 compare 1 min , = γ ( ) 0 2 = b i EECS 240 Lecture 5: Biasing © 2004 B. Boser 6 Cascoding

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EECS 240 Lecture 5: Biasing © 2004 B. Boser 7 Output Resistance EECS 240 Lecture 5: Biasing © 2004 B. Boser 8 Bias V* = 196.9mV Vds1 = 616mV Vgs2 = 884mV
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