L03 lecture - MOSFET Models for Design SPICE For...

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EECS 240 Lecture 3: MOSFET Models © 2004 B. Boser 1 MOSFET Models for Design SPICE – For verification – BSIM – Device variations Hand analysis – Square law model – Small-signal model – Design criteria Challenge – Complexity / accuracy tradeoff – How can we accurately design when large signal models suitable for hand analysis are off by 50% and more? EECS 240 Lecture 3: MOSFET Models © 2004 B. Boser 2 Models for Designers • Perspective –Phys ics – Simulator: accuracy & efficiency – Design: • relate device characteristics to circuit specifications • E.g. speed, gain, power dissipation • “Short-channel effects” – Square-law model – BSIM-X – Models for design must be simple & accurate
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EECS 240 Lecture 3: MOSFET Models © 2004 B. Boser 3 BSIM 3v3 Model • Supported by most simulators • Accurate down to L=0.25 µ m and below • BSIM 4 for even smaller devices • 100 parameters per device • 16 pages of equations • Download 0.35 µ m libraries from web • Good for verification (and optimization?) • Bad for design EECS 240 Lecture 3: MOSFET Models © 2004 B. Boser 4 Device Variations • Run-to-run parameter variations: – E.g. implant doses, layer thickness – Affect V TH , µ , C ox , R ± , … – How model in SPICE? • Nominal / slow / fast parameters – E.g. fast: low V TH , high µ , high C ox , low R ± – Combine with supply extremes – Pessimistic but numerically tractable Æ improves chances for working Silicon
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EECS 240 Lecture 3: MOSFET Models © 2004 B. Boser 5 Square-Law Model Large signal model – Predicts device current as a function of terminal voltages Accurate for devices with – Long channel L > 5 µ m – Thick oxide t ox > 50nm Qualitative correct predictions – Regions of operation Small signal parameters more important for analog design EECS 240 Lecture 3: MOSFET Models © 2004 B. Boser 6 Regions of Operation – Square Law Model saturation Linear / triode region strong inversion weak inversion TH GS V V < ( ) DS V TH GS L W ox D V V V C I DS 2 = µ TH GS V V TH GS DS V V V < TH GS DS V V V ( ) 2 2 1 TH GS L W ox D V V C I = ( ) 43 42 1 t DS t V DS V t nV GS V V V L W S D e e I I >> = for 1 0 1 C T q T k V o B t 17 at mV 25 = = region on transiti mV 100
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EECS 240 Lecture 3: MOSFET Models © 2004 B. Boser 7 Subthreshold Conduction (weak inversion) •L i k e B J T • n > 1: base controlled by capacitive divider –0 . 3 5 µ m CMOS: n = 1.5 •“ s l o w : –“ l a r g e C GS for “little” current drive (see later) • Increasingly common: – Low power – Submicron L means “high speed” even in weak inversion • Poor matching: –V TH mismatch amplified exponentially – Avoid in mirrors, low-offset differential pairs EECS 240 Lecture 3: MOSFET Models © 2004 B. Boser 8 “Short Channel” Effects •V TH decreases for small L – Large offset for diff pairs with small L • Mobility reduction: – Velocity saturation – Vertical field (small t ox =6.5nm) ¾ Reduced I D , g m increase slower than rt-I D
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This note was uploaded on 08/01/2008 for the course EECS 240 taught by Professor Boser during the Spring '04 term at University of California, Berkeley.

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L03 lecture - MOSFET Models for Design SPICE For...

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