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L16 lecture - Device Matching Mechanisms Spatial effects...

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EECS 240 Lecture 16: Matching and Layout B. Boser 1 Device Matching Mechanisms Spatial effects – Wafer-to-wafer Long range • Gradients Short range • Statistics Circuit effects Differential structures Differential pair Current mirror – Bias Layout effects EECS 240 Lecture 16: Matching and Layout B. Boser 2 Mismatch Model What is modeled? – Short-range, random processes, e.g. Dopant fluctuations Mobility fluctuations Oxide trap variations What is NOT modeled? – Batch-to-batch or wafer-to-wafer variations – Long-range effects such as gradients – Electrical, lithographic, or timing offsets
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EECS 240 Lecture 16: Matching and Layout B. Boser 3 References M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid- State Circuits, vol. 24, pp. 1433 - 1439, October 1989. Mismatch model Statistical data for 2.5 µ m CMOS Jeroen A. Croon, Maarten Rosmeulen, Stefaan Decoutere, Willy Sansen, Herman E. Maes; An easy-to-use mismatch model for the MOS transistor , IEEE Journal of Solid-State Circuits, vol. 37, pp. 1056 - 1064, August 2002. – 0.18 µ m CMOS data Qualitative analysis of short-channel effects on matching EECS 240 Lecture 16: Matching and Layout B. Boser 4 Mismatch Statistics Composed of many single events E.g. dopant atoms Individual effects are small Æ linear superposition applies Correlation distance << device dimensions Æ Mismatch has Gaussian distribution, zero mean
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EECS 240 Lecture 16: Matching and Layout B. Boser 5 MOSFET Mismatch Parameter Experiment: Experimental result applies to one particular configuration What about: Device size W L Area – Bias V GS Physical proximity – … Need parameterized model M2 M1 % 1 = D D I I EECS 240 Lecture 16: Matching and Layout B. Boser 6 Geometry Effects ( ) 2 2 2 2 x P P D S WL A P + = σ ( ) layout centroid - common for 0 : parameter, distance measured : parameter area measured : centers device between distance : area gate active : P of deviation standard : 2 P P x S A D WL P σ
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EECS 240 Lecture 16: Matching and Layout B. Boser 7 Example: V TH ( ) 2 2 , 2 , 0 2 0 0 x V P V P TH D S WL A V TH TH + = σ process) CMOS μm 5 . 2 ( m mV 35 m mV 30 , , µ µ PMOS P NMOS P A A EECS 240 Lecture 16: Matching and Layout B. Boser 8 Drain Bias, V DS V TH0 virtually independent of V DS
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EECS 240 Lecture 16: Matching and Layout B. Boser 9 Back-Gate Bias, V SB Pair 3 exhibits significant V SB dependence Why?
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