hw2 - s =0 of a 100/0.5 NMOS transistor in a common-source...

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1 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Problem Set 2 EECS 240 B. E. BOSER Due Tuesday, February 17, 2003 SPRING 2004 1. Choose the transistor dimensions and drain current to meet a 100MHz unity-gain requirement with minimum power dissipation. Verify with SPICE (use a large resistor and voltage source to bias the gate). Note: perusing graphs of I D versus V*, you can solve this problem with reasonable accuracy (few percent) without "trial and error" SPICE runs. 2. a) Integrate the input referred flicker noise for R
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Unformatted text preview: s =0 of a 100/0.5 NMOS transistor in a common-source configuration from 1Hz to 1GHz. Specify your result in Volts rms. Use V*=250mV and g m =50 S. b) Same, but use 1 year as the lower integration limit. c) State the increase in dB. Do you need to multiply by 10 or by 20? d) Find the factor M by which W and I D must be increased (keeping g m /I D constant) to accommodate the lower integration limit without an increase of the total noise. W/L V* = 200mV C s = 100fF V DD V o V i C L 5pF...
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This note was uploaded on 08/01/2008 for the course EECS 240 taught by Professor Boser during the Spring '04 term at University of California, Berkeley.

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