Unformatted text preview: s =0 of a 100/0.5 NMOS transistor in a common-source configuration from 1Hz to 1GHz. Specify your result in Volts rms. Use V*=250mV and g m =50 µ S. b) Same, but use 1 year as the lower integration limit. c) State the increase in dB. Do you need to multiply by 10 or by 20? d) Find the factor M by which W and I D must be increased (keeping g m /I D constant) to accommodate the lower integration limit without an increase of the total noise. W/L V* = 200mV C s = 100fF V DD V o V i C L 5pF...
View
Full Document
- Spring '04
- Boser
- Computer Science, Electrical Engineering, Integrated Circuit, Transistor, Volt, UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences
-
Click to edit the document details