# hw1 - mismatch i.e ∆ I/I ref< 0.01 Ignore all other...

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1 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Problem Set 1 EECS 240 B. E. BOSER Due Tuesday, February 3, 2004 SPRING 2004 Use the EECS240 0.35 µ m CMOS process in all home works and projects unless noted otherwise. 1. Design a PMOS common-source stage driving a 10pF load with 50MHz unity-gain bandwidth. Choose L=1 µ m, V*=200mV, and use an ideal current source load. Determine the device width and verify the bandwidth with SPICE. Also plot the small-signal gain a v0 =dV o /dV i as a function of V o . 2. For the current mirror below, calculate the maximum value of R that results in less than one percent
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Unformatted text preview: mismatch, i.e. ∆ I/I ref < 0.01. Ignore all other sources of current mismatch. Both transistors are the same size. a) Bias both transistors at V*=500mV. b) Same, but bias the transistors in weak inversion (n=1.5). Draw up instructions for the layout draftsman to meet the resistance constraints, if needed. 3. What is the minimum drain current needed to bias a 10/0.35 NMOS device in strong inversion? For the device to be clearly in strong inversion, V* must be at least 150mV. R I ref = 100 µ A I o...
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## This note was uploaded on 08/01/2008 for the course EECS 240 taught by Professor Boser during the Spring '04 term at Berkeley.

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