ps13 - UNIVERSITY OF CALIFORNIA College of Engineering...

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1 UNIVERSITY OF CALIFORNI A College of Engineerin g Department of Electrical Engineerin g and Computer Science s Homework 13 EECS 42/100 B. E. BOSER SPRING 2008 1. Design a finite state machine (FSM) for a vending machine controller. The vending machine accepts $1 bills and sells juice for $1 and cake for $2. The state machine has the following inputs and outputs: Inputs: $1, req_juice, req_cake, refund Outputs: ret_$1, ret_$2, drop_juice, drop_cake a. Find the minimum number of states required for implementing the FSM. How many bits are required to represent them? b. Draw a diagram for the FSM labeling the inputs, outputs, and clock signal. c. If the combinational logic is realized with a nonvolatile memory, what is the size required (number of address and output bits)? d. Draw the state transition diagram of the FSM (one bubble for each state and with labeled transition arrows between). e.
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This note was uploaded on 08/01/2008 for the course EE 42/100 taught by Professor Boser during the Spring '08 term at University of California, Berkeley.

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ps13 - UNIVERSITY OF CALIFORNIA College of Engineering...

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