ps12 - UNIVERSITY OF CALIFORNIA College of Engineering...

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UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EE 42 / 100 Problem Set 12 Spring 2008 1. State the conditions for a logic gate to be “valid” (i.e. operate correctly for all possible logic input states). 2. Design a transistor-level circuit that implements a logic “NOR”. This gate is used in the ALU (arithmetic and logic unit) of a microprocessor. Its output is capacitively loaded as shown in the diagram below. The capacitance comes from the input of other gates connected to the output of the NOR gate and from wiring parasitics. The propagation delay of the gate is defined as the worst case delay incurred when any of the two inputs A or B changes (logic 0 1 or 0 1) for the output Y of the gate to reach 90 % of its final value. Model the transistors in the gate with 200 Ω resistors in the on-state, and open circuits in the off-state. Calculate the propagation delay of the gate for low to high and high to low transitions of the
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This note was uploaded on 08/01/2008 for the course EE 42/100 taught by Professor Boser during the Spring '08 term at University of California, Berkeley.

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ps12 - UNIVERSITY OF CALIFORNIA College of Engineering...

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