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SPIEv2record - 1 TCAM Core Design in 3D IC for Low TCAM...

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Unformatted text preview: 1 TCAM Core Design in 3D IC for Low TCAM Core Design in 3D IC for Low Matchline Capacitance and Low Power Matchline Capacitance and Low Power Eun Chu Oh, Paul Franzon {ecoh,[email protected] , +1.919.515.7351 Department of Electrical and Computer Engineering, North Carolina State University December 11, 2006- SPIE Smart Materials, Nano- and Micro-Smart System Symposium - 2 Outline Outline 3D IC Technology and Design Content Addressable Memory Basics Design Alternatives and Tradeoffs 3D CAM Design Conclusions 3 3D IC Technology 3D IC Technology Integrating multiple tiers of silicon using vertical vias as interconnect Several technologies becoming available: SOI and Bulk CMOS Via sizes down to under 2 μ m Very high via yields demonstrated E.g. MIT Lincoln Labs 3-tier SOI Technology: IC2 Wafer-1 Handle Silicon IC3 Tier 3 Tier 1 Tier 2 3D inter-tier vias 4 Technology Technology (To scale) Lincoln Labs SOI Process “Vias last” process Tezzaron Bulk CMOS Process “Vias” first and Cu interfaces 5 Alternatives Alternatives Wafer-stacked processing Highest via density Limits substrate technology choices Die-on-wafer Lower via density More flexible choices ◊ E.g. III-V on Silicon c/- RTI c/- Ziptronix 6 Applications of 3D ICs Applications of 3D ICs Imagers & Vision Put electronics under pixel ◊ 100% Fill factor ◊ In-situ processing Memories High bandwidth, Low latency Memory on logic very attractive Processors and Circuits E.g. This talk Miniaturization alone is NOT a driver for 3D ICs Better done as a 3D package c/- MIT LL c/- Toshiba 7 Limitations of 3D ICs Limitations of 3D ICs Thermal Increased heat density Yield Management Can not test and repair before integration Each tier must be high yielding or you must have some level of defect tolerance Cost Additional cost for each added tier is equivalent to about 2 extra metal layers Must be justified against alternative methods of meeting system goal 8 3D IC Program at NCSU 3D IC Program at NCSU With Michael Steer, Rhett Davis CAD Tools Based around Cadence and Mechanica 3D Packaging At NCSU and with Irvine Sensors Application Exploration Circuits, e.g. 3D TCAM SOCs, e.g. 3D multiprocessor Systems, e.g. Synthetic Aperture Radar Synthesis Result (normal netlsit) Partition (use metis) Floorplan...
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This note was uploaded on 08/01/2008 for the course ECE 464 taught by Professor Chandra during the Spring '08 term at N.C. State.

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SPIEv2record - 1 TCAM Core Design in 3D IC for Low TCAM...

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