CD4007C - CD4007C Dual Complementary Pair Plus Inverter...

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October 1987 Revised January 1999 CD4007C Dual Complementary Pair Plus Inverter © 1999 Fairchild Semiconductor Corporation DS005943.prf www.fairchildsemi.com CD4007C Dual Complementary Pair Plus Inverter General Description The CD4007C consists of three complementary pairs of N- and P-channel enhancement mode MOS transistors suit- able for series/shunt applications. All inputs are protected from static discharge by diode clamps to V DD and V SS . For proper operation the voltages at all pins must be con- strained to be between V SS - 0.3V and V DD + 0.3V at all times. Features Wide supply voltage range: 3.0V to 15V High noise immunity: 0.45 V CC (typ.) Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Note: All P-channel substrates are connected to V DD and all N-channel substrates are connected to V SS . Top View Order Number Package Number Package Description CD4007CM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow CD4007CN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS–001, 0.300” Wide
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This note was uploaded on 08/06/2008 for the course ECE 137AB taught by Professor Rodwell during the Winter '08 term at UCSB.

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CD4007C - CD4007C Dual Complementary Pair Plus Inverter...

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