lab_hints

lab_hints - Lab Hints How to reduce the degree of effort in...

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1 Lab Hints How to reduce the degree of effort in testing lab assignments GENERAL WIRING PARASITICS. ......................................................................................................... 2 OSCILLATION. ........................................................................................................................................... 3 ............................... 3 SHARING OF GROUND CONNECTIONS ON THE BENCH . ................................................................................. 3 COUPLING BETWEEN INPUT AND OUTPUT THOUGH DISORGANIZED WIRING. ................................................ 5 OSCILLATION DUE TO CAPACITIVE LOADS. .................................................................................. 6 OSCILLATION DUE TO CIRCUIT CONSTRUCTION. ....................................................................... 6 GROUND SYSTEM INDUCTANCE . ................................................................................................................. 6 POWER SUPPLY BYPASS CAPACITORS. ......................................................................................................... 6 WIRING PARASITICS ON THE BOARD . .......................................................................................................... 7 CIRCUIT CONSTRUCTION. .................................................................................................................... 7 COPPER-CLAD GROUND-PLANE CIRCUIT BOARD . ........................................................................................ 7 NOT COPPER-CLAD GROUND-PLANE CIRCUIT BOARD. ................................................................................. 8 PROTO-BOARD. ........................................................................................................................................... 8 GENERALLY . .............................................................................................................................................. 8
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2 General Wiring parasitics On a circuit diagram, wires appear as simple lines, like so The voltages are equal at 2 wire ends, and the current entering on one end equals the current leaving on the other. This ignores the electromagnetic nature of the wires, and is approximately true only if the wires are very short. ECE144A gives a full treatment of this problem, and 145ab covers transistor circuit design including the effect. What follows below is approximate. Real wires (above) have inductance per unit length (both self-inductance and mutual inductance between nearby wires) and capacitance per unit length (both to ground and to nearby wires. How big is the effect ? A typical wire has ~50 pF/meter capacitance to ground and ~500
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lab_hints - Lab Hints How to reduce the degree of effort in...

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