Mar23 - CSE398: Network Systems Design Instructor: Dr....

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Unformatted text preview: CSE398: Network Systems Design Instructor: Dr. Liang Cheng Department of Computer Science and Engineering P.C. Rossin College of Engineering & Applied Science Lehigh University March 23, 2005 Instructor: Dr. Liang Cheng CSE398: Network Systems Design 03/23/05 Outline Recap Complexity of network processor design Lab time log Network processor architectures Summary and homework Instructor: Dr. Liang Cheng CSE398: Network Systems Design 03/23/05 Network Processor Architectures Primary architecture characteristics Packet flow Software architecture Assigning functionality to processor hierarchy Instructor: Dr. Liang Cheng CSE398: Network Systems Design 03/23/05 Primary Characteristics Processor hierarchy Memory hierarchy Internal transfer mechanisms External interface and communication mechanisms Special-purpose hardware Polling and notification mechanisms Concurrent and parallel execution support Programming model and paradigm Hardware and software dispatch mechanisms Instructor: Dr. Liang Cheng CSE398: Network Systems Design 03/23/05 Processing Hierarchy One or more embedded RISC processors One or more specialized coprocessors Multiple I/O processors One or more fabric interfaces One or more data transfer units Instructor: Dr. Liang Cheng CSE398: Network Systems Design 03/23/05 Processor Hierarchy Contd Type Programmable? On Chip? General purpose CPU y possible Embedded processor y typical I/O processor y t Coprocessor n t Fabric interface n t Data transfer unit n t Framer n possible Physical transmitter n possible Instructor: Dr. Liang Cheng CSE398: Network Systems Design 03/23/05 Memory Hierarchy Memory measurements Random access latency Sequential access latency Throughput Cost Internal External Instructor: Dr. Liang ChengInstructor: Dr....
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Mar23 - CSE398: Network Systems Design Instructor: Dr....

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