Mar23 - CSE398 Network Systems Design Instructor Dr Liang...

Info icon This preview shows pages 1–9. Sign up to view the full content.

View Full Document Right Arrow Icon
CSE398: Network Systems Design Instructor: Dr. Liang Cheng Department of Computer Science and Engineering P.C. Rossin College of Engineering & Applied Science Lehigh University March 23, 2005
Image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Instructor: Dr. Liang Cheng CSE398: Network Systems Design 03/23/05 Outline Recap Complexity of network processor design Lab time log Network processor architectures Summary and homework
Image of page 2
Instructor: Dr. Liang Cheng CSE398: Network Systems Design 03/23/05 Network Processor Architectures Primary architecture characteristics Packet flow Software architecture Assigning functionality to processor hierarchy
Image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Instructor: Dr. Liang Cheng CSE398: Network Systems Design 03/23/05 Primary Characteristics Processor hierarchy Memory hierarchy Internal transfer mechanisms External interface and communication mechanisms Special-purpose hardware Polling and notification mechanisms Concurrent and parallel execution support Programming model and paradigm Hardware and software dispatch mechanisms
Image of page 4
Instructor: Dr. Liang Cheng CSE398: Network Systems Design 03/23/05 Processing Hierarchy One or more embedded RISC processors One or more specialized coprocessors Multiple I/O processors One or more fabric interfaces One or more data transfer units
Image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Instructor: Dr. Liang Cheng CSE398: Network Systems Design 03/23/05 Processor Hierarchy – Cont’d Type Programmable? On Chip? General purpose CPU y possible Embedded processor y typical I/O processor y t Coprocessor n t Fabric interface n t Data transfer unit n t Framer n possible Physical transmitter n possible
Image of page 6
Instructor: Dr. Liang Cheng CSE398: Network Systems Design 03/23/05 Memory Hierarchy Memory measurements Random access latency Sequential access latency Throughput Cost Internal External
Image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Instructor: Dr. Liang Cheng
Image of page 8
Image of page 9
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern