HW5_solved - EECS 170D Homework#5 Due in class Tuesday...

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EECS 170D Homework #5 Due in class Tuesday November 27 th , 2007 Unless otherwise stated, the following parameters are assumed for the MOS Transistors: Technology : 0.25 um V to (V) Gamma V 1/2 V Dsat (V) K’(A/V 2 ) Lambda(V -1 ) NMOS 0.43 0.4 0.63 115x10 -6 0.06 PMOS -0.4 -0.4 -1 -30X10 -6 -0.1 Problem #1: Sizing a chain of inverters. a. In order to drive a large capacitance (CL = 20 pF) from a minimum size gate (with input capacitance Ci = 10fF), you decide to introduce a two-staged buffer as shown below. Assume that the propagation delay of a minimum size inverter is 70 ps. Also assume that the input capacitance of a gate is proportional to its size. Determine the sizing of the two additional buffer stages that will minimize the propagation delay. b. If you could add any number of stages to achieve the minimum delay, how many stages would you insert? What is the propagation delay in this case? c. Describe the advantages and disadvantages of the methods shown in (a) and (b). d.
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This note was uploaded on 08/22/2008 for the course EECS 170 taught by Professor Eltawil during the Spring '08 term at UC Irvine.

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HW5_solved - EECS 170D Homework#5 Due in class Tuesday...

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