HW3_solved - p =7 or 1.75 μ m.25 μ m c Removing the PMOS...

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Homework #3 Solution #1 a) CD B A Y ) ( + = NMOS (W/L) A = (W/L) B = (W/L) C = (W/L) D = 12 PMOS (W/L) A = (W/L) B = 16 (W/L) C = (W/L) D = 8 b) The worst case t pHL happens when the internal node capacitances in the PDN (at the drains of C & D) are charged before the high to low transition. The initial states that can cause this are ABCD = [1010, 1110, 0110]. The final state is one of: ABCD = [1011, 0111]. The worst case t pLH happens when the internal node capacitance in the PUN is discharged before the low to high transition. CD must be on initially to guarantee that the charges are removed to ground. The input pattern that can cause this is: ABCD=[0111]->[0011]. #2 a) AB Out 00 1 01 0 10 0 11 1 This function is an XNOR. b) The PMOS device will be velocity saturated and the NMOS will be in triode. 0 ) 1 )( 5 . ( ) 1 )( 5 . ( ' ' = + - + + - o o GT o n DS Dsat GT Dsat p V V V V L W k V V V V L W k λ Solving for this will give an answer of (W/L)
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Unformatted text preview: p =7 or 1.75 μ m/.25 μ m. c) Removing the PMOS will cause the output node to float for AB=00. The PMOS pulls the output to a high state when it would otherwise be a high impedance state. #3 (The power supply for .18u is 1.8V however Microwind defaults to 2V, since we didn’t specify they had to change to 1.8V, both solutions are provided. Also, Microwind doesn’t give tools for finding exact values, so these answers are estimates.) a) Power Supply 1.8V VOH = 1.8V VOL = 0V VM=.92V VIH = 1.05V VIL = .75V NML = .75V NMH = .75V Power Supply 2V VOH = 2V VOL = 0V VM = 1.02V VIH = 1.15V VIL = .9V NML = .9V NMH = .85V b) Power Supply 1.8V tpHL = 26ps tpLH = 32ps Power Supply 2V tpHL = 29ps tpLH = 24ps #4 a) b) c)...
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This note was uploaded on 08/22/2008 for the course EECS 170 taught by Professor Eltawil during the Spring '08 term at UC Irvine.

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HW3_solved - p =7 or 1.75 μ m.25 μ m c Removing the PMOS...

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