Session_07 - UT D CS 6386 Telecommunications Software...

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Unformatted text preview: UT D CS 6386 Telecommunications Software Design Session 07 Switch & Router Architecture Introduction Switch A key component in voice networks (PSTNs) Main function is to connect voice circuits circuit switching Analogy? Router A key component in data networks (PSDNs) Main function is to direct packets packet switching Analogy? 2 1 PSTNs - Public Switching Telephone Networks 3 PSTNs Key Components Customer Premise Equipment Network Switches Local (class 5) Tandem (class 4) International Gateway Transmission equipment (OC-192, cross-connect, (OCcrossMux/DeMux, Mux/DeMux, etc.) Signaling equipment (STP, SCP) OAM&P equipment (Billing, Monitoring equipment) Network equipment for carriers: carrier grade 4 2 CPE Customer Premise Equipment Phone sets Key systems Serve a small number of lines Limited features PBX - Private Branch Exchange Full switching function at customer premise Under control of customer CENTREX PBX functionality implemented as features in the Central Office 5 PBX Architecture Analog Phones Digital Phones L I N E I/F PBX Switching System T R U N K I/F Local Switched Access IXC Special Access Private Lines Administration OAM&P Systems 6 3 PBX Design The PBX is a switching system with small capacity and a limited feature set Hence the design is usually centralized One processor can take care of all necessary functions of a switch There is no need for other processors Some modern PBX may have other auxiliary processors, but the number is small Can we design a PBX with a PC? What can be problems? 7 Switch Why Switching? The issue N persons each has a telephone, anyone must be able to talk to anyone else When A talk to B a voice circuit needs to be established between A and B But they do not talk all the time, i.e. circuit connection time is short Solution Direct line? Not practical if N is big A switch Connections are made dynamically when needed 8 4 Voice Switch Example Nortel's DMS SuperNode 9 Nortel's DMS SuperNode Hardware Architecture A functionally distributed, multiprocessing, multiprogramming, realsoft real-time, embedded system! 5 Function Distribution Signaling The Link Peripheral Processor (LPP) has units (processing elements) that perform signaling functions The LIU7 (Link Interface Unit for SS#7) is such a unit Terminating an SS#7 link from SS#7 network (from an STP or an SCPs) Preprocess SS#7 messages before forwarding them to the Computing Module (CM) or XA-Core XA11 Function Distribution Call Processing Call Processing function is performed at both the CM (Computing Module) and PM (Peripheral Module) The LCM (Line Control Module) carries out call processing for lines The LGC (Line Group Controller) handles call processing functions for a group of lines The SPM (Spectrum Peripheral Module) performs call processing function for trunks Replacing the DTC (Digital Trunk Controller) 12 6 Function Distribution Others The SDM (SuperNode Data Manager) handle billing preprocessing before sending billing data to a operating support system (OSS) The IOM (Input/Output Module) handles IO tasks, such as storage (to store loads) and terminal interfacing The MS (Message Switch) distributes messages to components of the switch It is by itself a packet switch The ENET (Enhance NET) is the switching fabric 13 Switching Fabric Time Division Switching Switching occurs in time domain Time slot interchange is the key idea Time slot interchange (TSI) Inputs are divided in to time slots Time slots are interchanged to get desired switching effect Key technique used in telephone switching fabric Implemented in hardware using VLSI technology 14 7 Time Division Switching Time Slot Interchange 15 Time Slot Interchange Example 4 3 2 1 1 2 3 4 2 4 1 3 Connections: (1,3) (2,1) (3,4) (4,2) Read and write to shared memory in different order 16 8 Time Slot Interchange Properties Simple to build, suitable for VLSI technology Main limitation: the time to read and write to time slot memory limits the number of ports a TSI can support For example: for a 100,000 ports TSI for a telephone switch Each port reads and writes one time slot worth of data to memory 8000 times per second (once every 125 ms) Number of operations per second : 100,000 x 8000 x2 Not possible with current memory technology Need to look to other techniques 17 Switching Fabric Space Division Switching Each sample takes a different path through the switch, depending on its destination Crossbar: Simplest possible space-division switch space Cross points can be turned on or off i n p u t s 18 outputs 9 Switching Fabric Crossbar connections: (1,2) (2,4) (3,1) (4,3) 1 2 3 4 4 19 1 2 3 Space Division Switching Crossbar Properties Advantages simple to implement simple control strict sense non-blocking non- Drawbacks number of cross points = N2 large VLSI space vulnerable to single faults 20 10 Switching Fabric Time and Space Division Switching A combination of time and space division switching is usually used to achieve higher port capacity 21 Switching Fabric Hardware Implementation 16k x 16k time/space switching fabric 22 11 Function Distribution The Computing Module The central nerve center of the system! Performs Call Processing System maintenance System management Interface with other sub-system, e.g. OAM&P subEtc... Can be uni-processor (BRISC) or multiunimultiprocessor (XA-Core) (XA High reliability and availability Has more than 30 millions line of code! 23 Nortel's DMS SuperNode CM Software Architecture 24 12 Voice Switches - What Next? Example: Nortel's Succession 25 Data Networks the Internet Core router The Internet Core Edge Router 26 13 Internet Router Examples Access routers e.g. ISDN, ADSL Core ATM switch 19" 19" Core router e.g. Cisco GSR 12416 27 ATM Switch Lookup cell VCI/VPI in VC table Replace old VCI/VPI with new Forward cell to outgoing interface Transmit cell onto link 28 14 Ethernet Switch Lookup frame destination address in forwarding table If known, forward to correct port If unknown, broadcast to all ports Learn source address of incoming frame Forward frame to outgoing interface Transmit frame onto link 29 Ethernet Switch/Router Examples Advances in hardware and software -> cheap Ethernet switches 30 15 SMC7004ABR Specs Ports Four 10Base-T/100BaseTX RJ-45 ports (auto-MDIX/MDI) One 10Base-T/100BaseTX Broadband WAN port One DB-9 port for PSTN/ISDN connection One DB-25 printer port Internet Sharing Methods Static IP, Dynamic IP, PPPoE, Dial-up networking Protocols TCP/IP, PPTP, IPSec (VPN) Topology Star Cabling Type 10Base-T: UTP/STP Category 3 or 5 100Base-TX: UTP/STP Category 5 or better Speed WAN: 10 Mbps (10Base-T Ethernet) 100 Mbps (100Base-TX Fast Ethernet) LAN: 10 Mbps (10Base-T Ethernet) or 100 Mbps (100Base-TX Fast Ethernet) server, NAT firewall Standards IEEE 802.3 31 IEEE 802.3u IP Router Lookup packet destination address in forwarding table If known, forward to correct port If unknown, drop packet Decrement TTL, update header checksum field Forward packet to outgoing interface Transmit packet onto link 32 16 Router Architecture Functional View Congestion Control Admission Control Routing Reservation Control Data Path Input Buffering Forwarding Output Scheduling 33 Router Architecture Data Path Two key router functions Maintain routing tables using routing protocols (RIP, OSPF, BGP) Forwarding (switching) packets from incoming to outgoing link 34 17 Router Architecture Input Port Functions Physical layer: bit-level reception Data link layer: e.g., Ethernet Decentralized switching given packet destination, lookup output port using routing table in input port memory goal: complete input port processing at `line speed' queuing: if packets arrive faster than 35 forwarding rate into switch fabric Router Architecture Routing Header Processing Data Hdr Data Hdr Lookup Update IP Address Header IP Address Next Hop Queue Packet 1M prefixes Off-chip DRAM Address Table Buffer Memory 1M packets Off-chip DRAM 36 18 Router Architecture Lookup (Forwarding) Engine Packet payload header Router Destination Address Routing Lookup Data Structure Forwarding Table Dest-network 65.0.0.0/8 128.9.0.0/16 Outgoing Port Port 3 1 149.12.0.0/19 7 37 Router Architecture Forwarding Table - Example Destination IP Prefix 65.0.0.0/8 128.9.0.0/16 142.12.0.0/19 Outgoing Port 3 1 7 142.12.0.0/19 Prefix length IP prefix: 0-32 bits 65.0.0.0/8 128.9.0.0/16 0 65.0.0.0 128.9.16.14 224 65.255.255.255 232-1 38 19 Router Architecture Lookup - Example (Incoming port, label) (Outgoing port, label) Memory IP addresses: 32 bits long 4G entries if one for each address The Search Operation is not a Direct Lookup 39 Router Architecture Routing Lookup Longest matching prefix 65.0.0.0/8 128.9.176.0/24 142.12.0.0/19 128.9.16.0/21 128.9.172.0/21 128.9.0.0/16 0 128.9.16.14 232-1 Routing lookup: Find the longest matching prefix (aka the most specific route) among all prefixes that match the destination address. 40 20 Router Architecture Required Lookup Rate Year Line LineLine-rate (Gbps) 0.622 2.5 10.0 40.0 40B packets (Mpps) 1.94 7.81 31.25 125 19981998-99 19991999-00 20002000-01 20022002-03 OC12c OC48c OC192c OC768c 31.25 Mpps 33 ns DRAM: 50-80 ns, SRAM: 5-10 ns 41 Router Architecture Forwarding Table Size Number of Prefixes 100000 90000 80000 70000 60000 50000 40000 30000 20000 10000 0 10,000/year 95 96 97 Year 98 99 00 42 Source: http://www.telstra.net/ops/bgptable.html 21 Router Architecture Input Port Queuing If fabric slower that input ports combined queueing may occur at input queues The Head-of-the-Line (HOL) blocking issue Head-of-the queued datagram at front of queue prevents others in queue from moving forward queueing delay and loss due to input buffer overflow! 43 Input Port Queueing Head of Line Blocking Issue Delay Load 58.6% 100% 44 22 Head of Line Blocking Issue 45 Head of Line Blocking Issue Virtual output queues 46 23 Input Port Queueing Virtual Output Queues Delay Load 100% 47 Router Architecture Switching Fabrics 48 24 Switching Fabric Memory First generation routers packets copied by a system processor speed limited by memory bandwidth (2 bus crossings per Memory datagram) Input Output Port Port System Bus Modern routers multiple processor input port processor performs lookup, copy into memory output processor copy to output port 49 Interconnects Centralized Shared Memory Input 1 Numerous work has proven and Output 1 made possible: Fairness Delay Guarantees Delay Variation Control Loss Guarantees Output 2 Guarantees Statistical Input 2 Input N Large, single dynamically allocated memory buffer: Output N per "cell" time N writes N reads per "cell" time. Limited by memory bandwidth. 50 25 Output Queueing How fast can we make centralized shared memory? 5ns SRAM Shared Memory 1 2 N 200 byte bus 5ns per memory operation Two memory operations per packet Therefore, up to 160Gb/s In practice, closer to 80Gb/s 51 Switching Fabric Bus Architecture Packets are forwarded from input port memory to output port memory via a shared bus Bus contention is the speed limiting factor switching speed limited by bus bandwidth 1 Gbps bus - Cisco 1900 sufficient speed for access and enterprise routers but not for regional or backbone 52 26 Switching Fabric Interconnection Networks Overcome bus bandwidth limitations Banyan networks and other interconnection networks initially developed to connect processors in multiprocessor systems Advanced design fragmenting datagram into fixed length cells switch cells through the fabric Example: Cisco 12000 switches Gbps through the interconnection network 53 Router Architecture Output Ports Buffering required when datagrams arrive from fabric faster than the transmission rate Scheduling discipline chooses among queued packets for transmission 54 27 Router Architecture Output Port Queueing buffering is needed when arrival rate via switch exceeds output line speed queueing delay loss due to output port buffer overflow! 55 FirstFirst-Generation IP Routers Single Processor and Memory Shared Backplane CPU Buffer Memory DMA DMA DMA Line Interface MAC Line Interface MAC Line Interface MAC Shared memory as switching fabric 56 28 SecondSecond-Generation IP Routers Buffer Memory on Line Cards CPU Buffer Memory DMA DMA DMA Line Card Local Buffer Memory MAC Line Card Local Buffer Memory MAC Line Card Local Buffer Memory MAC System bus as switching fabric, line cards has buffer memory 57 ThirdThird-Generation Routers Interconnect Fabric Switched Backplane Line Card Local Buffer Memory MAC CPU Card Line Card Local Buffer Memory MAC Interconnect as switching fabric 58 29 FourthFourth-Generation Routers Clustering and Multistage 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 11121314 1516 13 14 15 16 17 18 25 26 27 28 29 30 17 1819 20 21 22 2324252627 28 29 3031 32 7 8 9 10 11 12 19 20 21 22 23 24 31 32 59 Distributed, multiprocessor system! Router What Next? 60 30 ...
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This note was uploaded on 09/01/2008 for the course CS 6386 taught by Professor Nguyen during the Summer '08 term at University of Texas at Dallas, Richardson.

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