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Unformatted text preview: ECE/CS 314 Spring 2007 Homework 4 Solutions Homework Submission Policies 1. Show your work where appropriate. 2. Homework Assignments are done individually without calculators . 3. Homework must be typed and submitted in plain text or PDF format. No scanned PDF (or scanned ANYTHING) allowed. 4. All homework should be submitted through CMS. Under no circumstances should a submission be made by sending the completed assignments to a course staff by email, unless explicitly requested. (Make sure you are signed up for the class on CMS BEFORE the submission deadline.) 5. In general, late submissions will not be graded. However, if CMS is down prior to a deadline, please contact the course staff BEFORE the deadline and make a submission when the system is back up (it will not be penalized). 6. Questions may be directed to the ECE/CS 314 consultants. Problem 1. (10 points) The following circuit implements an 8bit adder using two carrylookahead adders, add4, and one groupcarry lookahead circuit, group_cla. Recall that the carrylookahead adders use the following logic formulas: si = ai^bi^ci gi = ai & bi pi = ai  bi c1 = g0  p0 & c0 c2 = g1  p1 & g0  p1 & p0 & c0 c3 = g2  p2 & g1  p2 & p1 & g0  p2 & p1 & p0 & c0 P = p3 & p2 & p1 & p0 G = g3  p3 & g2  p3 & p2 & g1  p3 & p2 & p1 & g0 The groupcarry lookahead circuit uses the P and G outputs from the carrylookahead adders and the CIN input and carrylookahead logic to calculate C4, C8, P_ALL and G_ALL, where C4 and C8 are group carry bits and P_ALL and G_ALL are the propagate and generate bits for the entire 8bit adder. A3 A4 A5 A6 A7 A0 A1 A2 B0 B1 B2 B3 B4 B5 B6 B7 CIN S0 S1 S2 S3 S4 S5 S6 S7 COUT G_ALL P_ALL a3 b3 a2 b2 a1 b1 a0 b0 c0 s3 s2 s1 s0 G P add4 a3 b3 a2 b2 a1 b1 a0 b0 c0 s3 s2 s1 s0 G P add4 G1 P1 G0 P0 C0 C8 C4 G_ALL P_ALL group_cla Find Boolean expressions for each of these 4 bits. a) C4 = G0  P0 & C0 b) C8 = G1  P1 & C4 = G1  P1 & (G0  P0 & C0) = G1  P1 & G0  P1 & P0 & C0 c) P_ALL = P1 & P0 d) G_ALL = G1  P1 & G0 Problem 2. (15 points) Consider the following sequence of LC314 instructions: 0: nand 1 2 3 ; reg 3 = ~(reg 1 & reg 2) 1: lw 2 4 8 ; reg 4 = Mem[reg 2+8] 2: add 1 5 5 ; reg 5 = reg 1 + reg 5 3: add 0 1 2 ; reg 2 = reg 0 + reg 1 4: sw 3 6 9 ; Mem[reg 3+9] = reg 6 5: nop 6: nop 7: nop 8: nop 9: nop Using the following diagram of the LC314 pipeline structure, PC Inst mem Register file M U X A L U M U X 1 Data mem + + M U X IF/ ID ID/ EX EX/ Mem Mem/ WB M U X Bits 02 Bits 1517 op dest offset valB valA PC PC target ALUR op dest valB op dest ALUR mdata eq? instruction 3 5 1 6 17 12 8 R2 R3 R4 R5 R1 R6 R0 R7 regA regB Bits 2123 data dest PC Inst mem Register file M U X A L U A L U M U X 1 Data mem + + M U X IF/ ID ID/ EX EX/ Mem Mem/ WB M U X Bits 02 Bits 1517 op dest offset valB valA PC PC target ALUR op dest valB op dest ALUR mdata eq?...
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 Spring '07
 MCKEE/LONG
 Virtual memory, Central processing unit, CPU cache, Translation lookaside buffer, Memory management unit

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