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ECE314sp07_HW4_solution

ECE314sp07_HW4_solution - ECE/CS 314 Spring 2007 Homework 4...

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ECE/CS 314 Spring 2007 Homework 4 Solutions Homework Submission Policies 1. Show your work where appropriate. 2. Homework Assignments are done individually without calculators . 3. Homework must be typed and submitted in plain text or PDF format. No scanned PDF (or scanned ANYTHING) allowed. 4. All homework should be submitted through CMS. Under no circumstances should a submission be made by sending the completed assignments to a course staff by email, unless explicitly requested. (Make sure you are signed up for the class on CMS BEFORE the submission deadline.) 5. In general, late submissions will not be graded. However, if CMS is down prior to a deadline, please contact the course staff BEFORE the deadline and make a submission when the system is back up (it will not be penalized). 6. Questions may be directed to the ECE/CS 314 consultants.

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Find Boolean expressions for each of these 4 bits. a) C4 = G0 | P0 & C0 b) C8 = G1 | P1 & C4 = G1 | P1 & (G0 | P0 & C0) = G1 | P1 & G0 | P1 & P0 & C0 c) P_ALL = P1 & P0 d) G_ALL = G1 | P1 & G0

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Problem 2. (15 points) Consider the following sequence of LC314 instructions: 0: nand 1 2 3 ; reg 3 = ~(reg 1 & reg 2) 1: lw 2 4 8 ; reg 4 = Mem[reg 2+8] 2: add 1 5 5 ; reg 5 = reg 1 + reg 5 3: add 0 1 2 ; reg 2 = reg 0 + reg 1 4: sw 3 6 9 ; Mem[reg 3+9] = reg 6 5: nop 6: nop 7: nop 8: nop 9: nop Using the following diagram of the LC314 pipeline structure, PC Inst mem Register file M U X A L U M U X 1 Data mem + + M U X IF/ ID ID/ EX EX/ Mem Mem/ WB M U X Bits 0-2 Bits 15-17 op dest offset valB valA PC PC target ALUR op dest valB op dest ALUR mdata eq? instruction 3 5 1 6 17 12 0 8 R2 R3 R4 R5 R1 R6 R0 R7 regA regB Bits 21-23 data dest Fill in the table on the following page with the appropriate values. The first one has been done for you. (I.e., the first cycle executed the instruction fetch of the “nand 1 2 3” instruction.) Note that initially Mem[i] = 123 for all values of i.
Pipline Register Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 IF/ID.PC 1 2 3 4 5 6 7 8 9 IF/ID.instruction nand 1 2 3 lw 2 4 8 add 1 5 5 add 0 1 2 sw 3 6 9 nop nop nop nop ID/EX.PC 0 1 2 3 4 5 6 7 8 ID/EX.valA 0 19 (or 17) 3 19 (or 17) 0 -4 (or -2) 0 0 0 ID/EX.valB 0 3 1 6 19 (or 17) 12 0 0 0 ID/EX.offset 0 3 8 5 2 9 0

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• Spring '07
• MCKEE/LONG
• Virtual memory, Central processing unit, CPU cache, Translation lookaside buffer, Memory management unit

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ECE314sp07_HW4_solution - ECE/CS 314 Spring 2007 Homework 4...

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