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l21_handouts_4up - Announcements Online Course Evals(DO IT...

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Unformatted text preview: Announcements Online Course Evals (DO IT, DO IT, DO IT): Wed 23 Apr -- Weds 7 May (FLEXGRADE!) http://www.engineering.cornell.edu/courseeval http://www.engineering.cornell.edu/courseeval CHECK THE NEWSGROUP before sending email Homework 6 due today, April 15 (tax day), 10p.m. Calculators allowed on Homework 6, Prelim 2 Project 4b due Thursday, April 17, 10p.m. Project 4c posted Thursday, April 17 Prelim2 April 22, 7:30, Uris Hall Auditorium Web page is at: http://sampaka.csl.cornell.edu/classes/ece314/ Remember This Slide? Copyright Sally A. McKee 2006 Copyright Sally A. McKee 2006 What You Need to Remember for Today SRAM (pretty fast) and DRAM (pretty slow) Adding caches reduces average memory latency Locality principles Memory hierarchy structure (we'll revisit this) Virtual memory (we'll revisit this) TLBs (we'll revisit this) Cache Design 101 Reg 100s Bytes 1 cycle access (early in pipeline) 1-3 cycle access L1 Cache (several KB) L3 becoming more common (sometimes VERY LARGE) L2 Cache (-32MB) 6-15 cycle access Memory pyramid Memory (128MB few GB) 50-300 cycle access Disk (Many GB) Millions cycle access! Copyright Sally A. McKee 2006 These are rough numbers: mileage may vary for latest/greatest Caches USUALLY made of SRAMMcKee 2006 Copyright Sally A. 1 I/O Facts Disks are slow. Why? Physical reasons? Design reasons? Disks Evolution (Revolution?) Networks are slow. Why? Physical reasons? Design reasons? Copyright Sally A. McKee 2006 Copyright Sally A. McKee 2006 Disks Magnetic storage Moving head Sort of like old LP record Mechanical head moves to the right track, waits for sector to rotate under Virtual Memory How do we fit several programs in memory at once? How does the assembler/compiler know what addresses are OK to use? Multiprogramming allows >1 program to run "at the same time" Who keeps track of what's where? Tracks, just like LP Sectors divide up tracks Copyright Sally A. McKee 2006 Copyright Sally A. McKee 2006 2 Virtual Memory (initial view) Pages Divide memory into chunks For caches, lines or blocks For main memory, pages x, y, and s would have been in one of these places, so would have had different addrs Assume virtual == physical page size 4KByte pages for now 0x00000000 is invalid (remember why?) 0x00001000 0x00002000, . . . 0x00001000 Copyright Sally A. McKee 2006 Copyright Sally A. McKee 2006 high addresses A More Detailed View of VM (not to scale) operating system lives up here bookkeeping page (OS access) PROCESS PAGE TABLE (OS access only) initial stack page Virtual to Physical Mapping 0x40000000 Don't need to fill in all these page table entries, since we (probably) won't use all these addresses ... initial heap page uninitialized data pages initialized data pages code pages OS/kernel keeps track of open files, where process is in those files, and anything else user shouldn't muck with kernel calls this "BSS" 0x00000000 translation from virtual to physical (DRAM) memory 0x00000000 low addresses OS makes V=0: catch ptrs=0 Copyright Sally A. McKee 2006 kernel calls this "text" virtual memory page table does this Copyright Sally A. McKee 2006 physical memory (DRAM) 3 Virtual to Physical Mapping virtual address 0x00001000 physical address 0x0000C000 00000000000000000001 00000000 00 00 page number translation page offset Page Table What if the page table entry is invalid? Page misses (Fig 7.22 greatly oversimplifies) Code/Text Static variables/Globals variables/Globals Stack Heap Page table? 00000000000000001101 00000000 00 00 page number page offset page offset doesn't change! Swapping (need replacement policy, probably LRU) Copyright Sally A. McKee 2006 Copyright Sally A. McKee 2006 Page Table: OS's Control over What's Accessed and How virtual page number page offset V D R X K Page Table Each process's page table is in memory But memory is SLOW! What can we do? page table holds: physical page numbers bookkeeping info valid (usable) dirty (updated) read-only/writeable executable (code?) OS/kernel access only physical page number page offset Copyright Sally A. McKee 2006 Copyright Sally A. McKee 2006 4 Translation Lookaside Buffer Why "TLB"? Cache for PTEs Looks a lot like a little page table Usually fully associative tag physical addr v dr x k TLBs It's just cache for our current working set of Pate Table Entries Replacement can be hardware or software Simple TLB hardware replacement easy Can have other associativities, multiple levels When entry evicted, bookkeeping bits must be updated in page table Copyright Sally A. McKee 2006 Copyright Sally A. McKee 2006 TLBs Size: 16-512 entries 16Tag is virtual page number Need to track LRU information (this is the ref bit in the book) TLB lookup takes place in parallel with cache access Typically high hit rates (miss < 1% of time) L1 cache indexed by virtual addresses L2 can be virtual or physical (if TLB hit, we'll have physical address in time for lookup) Copyright Sally A. McKee 2006 TLB What if entry is invalid? Not present? TLB misses If present, get PTE from memory If not present, OS handles page fault Can be very expensive! Many memory accesses Need to transfer control to OS Possibly disk accesses or network accesses Copyright Sally A. McKee 2006 5 What if CPU Generates Untranslatable Address? TLB miss? Check Page Table Page Table Page not Valid? Create it Entry won't be valid, though More Complications Unaligned accesses (BAD) Pages have to be mapped by OS into its own space in order to do most of this work If miss in TLB, SLOW SLOW SLOW Page Table Entry (PTE) not Valid? Find DRAM page Fill it appropriately Create PTE and insert in Page Table Copyright Sally A. McKee 2006 Copyright Sally A. McKee 2006 What if CPU Generates Untranslatable Address? Entry exists in Page Table, but Access Bits Wrong Could be trying to write a code page (BAD) Could be trying to read/write an OS-only page (BAD) OSCould be trying to execute a page that isn't code (BAD) How OS Tracks DRAM Page Usage typedef struct Page Page; Page; struct Page { Page *next; Page *prev; *prev; short type; long qid; // file from which this page came qid; long va; // virtual address of base page va; Lock lock; // prevents other accesses while in use lock; short ref; // how many procs are using this page? } OS keeps list of ALL DRAM PAGES in use Copyright Sally A. McKee 2006 BUT ... If two processes share a clean data page, and one needs to write ... Share UNTIL one process writes, then make a copy for the writing process Get DRAM page, copy data Set D bit Let writing process continue w/ its own copy Called "Copy on Write" (example of Lazy Evaluation) Copyright Sally A. McKee 2006 6 How OS Tracks Processes typedef struct Proc Proc; struct Proc { // all state required to get process running again // e.g., how to find Page Table // e.g., how to find Register Values // most other info is saved in process itself! } Copyright Sally A. McKee 2006 Interrupts/Exceptions Could be legitimate, could signal error condition Clock interrupt (timeslice completed or process doing I/O, so wake up (timeslice someone else) Missing PTE (could be OK) Bad address (not OK) Divide by 0 (never OK) ALU overflow when not allowed (not OK) Control transfers to OS ID of interrupt or exception is saved where OS can find it (could (could be OS's own stack) Interrupt vector contains addresses of OS processes to handle conditions ID says which entry in interrupt vector to jump to (execute) If Interrupt, control eventually returns to user process If Exception, process gets killed Copyright Sally A. McKee 2006 7 ...
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