lecture 12

lecture 12 - 1 Announcements • Homework 3 has been posted...

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Unformatted text preview: 1 Announcements • Homework 3 has been posted ue Tue Mar 4 10:00pm – Due Tue., Mar 4, 10:00pm – Verilog option (hw3b), problems 3,4,6 may be handed in Tue., Mar 11, 10:00pm • Homework 4 to be posted today – Due Tue., Mar 11, 10:00pm roject 3 has been posted ECE/CS 314 • Project 3 has been posted – Due Tue., Mar 26, 10:00pm, but don’t delay starting! • Prelim 1 March 13 @ 7:30pm, in the Uris Hall Auditorium Announcements • HKN tutoring – Monday 7-9pm – Tuesday 7-9pm Í NEW!!! ECE/CS 314 Hennessy and Patterson • Read CD – Read Appendix B.1-B-5 (Done) ead Appendix B 6 11 (Done) – Read Appendix B.6-B.11 (Done) – Read (again) Appendix B.6 (Done) • Read Chapter 5 – Read 5.1-5.5 for (DONE) – Read 5.6, 5.9-5.11 for fun • Read Espresso Tutorial (link on course web page) • Read Verilog Process Tutorial and Verilog Tools ummary (links on Project 3 web page ECE/CS 314 summary (links on Project 3 web page • Read Chapter 6 – Read 6.1-6.3 for Thursday Simple Single Cycle Datapath IF ID MEM WB EX Brch 4 [15:11] [20:16] [25:21] Inst Mem Iaddr Iin 15:11] Reg File RA RB A B W RW WE Ctrl P C [15:0] 1 ExtImm A L U Data Mem Daddr Dout Din DMC 1 [10:6] 1 1 <<2 ECE/CS 314 [20:16] 1 [15:11] add, sub, and, or, xor, nor, slt, beq, bne, blez, bgtz, bltz, bgez, addi, slti, andi, ori, xori, lw, sw, sll, srl, sra Control Unit 2 Improvements? • How can we do better? • What are the limitations of this design? • What will limit it’s speed? • Why don’t we just stop here?...
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lecture 12 - 1 Announcements • Homework 3 has been posted...

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