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lecture 13 - Announcements Homework 3b(Verilog option Due...

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1 Announcements Homework 3b (Verilog option) Due Tue Mar 11 10:00pm – Due Tue., Mar 11, 10:00pm – Verilog problems 3,4,6 Homework 4 – Due Tue., Mar 11, 10:00pm Project 3 D T M 26 10 00 b t d ’t d l t ti ! ECE/CS 314 – Due Tue., Mar 26, 10:00pm, but don’t delay starting! Prelim 1 March 13 @ 7:30pm, in the Uris Hall Auditorium Hennessy and Patterson Read Chapter 5 Read 5.1-5.5 for (DONE) Read 5 6 5 9 5 11 for fun Read 5.6, 5.9-5.11 for fun Read Espresso Tutorial (link on course web page) Read Verilog Process Tutorial and Verilog Tools summary (links on Project 3 web page) Read Chapter 6 Read 6.1-6.3 (Done) Read 6.4-6.6 for Thursday Read 6 8 6 12 for fun (for now) ECE/CS 314 Read 6.8-6.12 for fun (for now) Clock Cycles per Instruction Single-Cycle Processor [Average of] 1 clock cycle per instruction – [Average of] 1 clock cycle per instruction Multi-Cycle Processor – Must know distribution of different types of instructions executed – Compute average E g suppose 10% take 3 cycles 70% take 4 cycles ECE/CS 314 E.g., suppose 10% take 3 cycles, 70% take 4 cycles, and 20% take 5 cycles Average of 4.1 clock cycles per instruction In this case, multi-cycle is better if the clock speed is at least 4.1 times faster than equivalent single-cycle Carry Lookahead Adders a b cin p g s a b cin p g s a b cin p g s a b cin p g s a b cin p g s a b cin p g s a b cin p g s a b cin p g s a b cin p g s a b cin p g s a b cin p g s a b cin p g s c4 c3 c2 c1 P G c0 c4 c3 c2 c1 P G c0 c4 c3 c2 c1 P G c0 C4 C3 C2 C0 ECE/CS 314 C1 P G
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