l14_handouts_4up - Announcements Homework 3b (Verilog...

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1 Announcements • Homework 3b (Verilog option) ue Today Mar 11 10:00pm – Due Today, Mar 11, 10:00pm – Verilog problems 3,4,6 • Homework 4 – Due Today, Mar 11, 10:00pm • Project 3 ECE/CS 314 – Due Tue., Mar 26, 10:00pm, but don’t delay starting! • Prelim 1 March 13 @ 7:30pm, in the Uris Hall Auditorium Announcements • If you asked for a make-up exam and did not ceive an email from me this morning ontact receive an email from me this morning, Contact me ASAP!! • Prelim will cover – Lectures through 3/6 (but no detailed questions on pipelining) – Homeworks 1-4 (HW4 solutions will be posted) class review on Thursday ECE/CS 314 • In class review on Thursday – Bring questions!!! • NO CALCULATORS!!! Hennessy and Patterson • Read Chapter 5 – Read 5.1-5.5 for (DONE) ead56 59 11forfun – Read 5.6, 5.9-5.11 for fun • Read Espresso Tutorial (link on course web page) • Read Verilog Process Tutorial and Verilog Tools summary (links on Project 3 web page) • Read Chapter 6 – Read 6.1-6.3 (Done) Read 6.4-6.6 for Today ead 6 8 12 for fun (for now) ECE/CS 314 Read 6.8-6.12 for fun (for now) Pipelined Datapath IF ID MEM WB EX Brch 4 PC+4 [20:16] [25:21] Inst Mem Iaddr Iin 15:11] Reg File RA RB A B W RW WE Ctrl P C [15:0] 0 1 ExtImm A L U Data Mem Daddr Dout Din DMC 0 1 [10:6] 0 1 INS A B SHA M IMM MDATA ALUR WDATA 0 1 <<2 ECE/CS 314 [20:16] 0 1 Control Unit DR T CTRL C. add, sub, addi, beq, bne, lw, sw, sll, srl, sra
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2 Pipeline Hazards • Structural Hazard wo different instructions try to use the same – Two different instructions try to use the same hardware during the same clock cycle • Data Hazard – Instruction cannot execute because data that it needs is not available ontrol Hazard ECE/CS 314 Control Hazard – Starting execution of the wrong instruction due to a branch decision that hasn’t been made yet Pipelined DP/with Forwarding IF ID MEM WB EX Brch 4 PC+4 [20:16] [25:21] Inst Mem Iaddr Iin 15:11] Reg File RA RB A B W RW WE Ctrl P C [15:0] 0 1 ExtImm A L U Data Mem Daddr Dout Din DMC 0 1 [10:6] 0 1 0 1 <<2 INS A B SHA M IMM MDATA ALUR WDATA 0 1 2 0 1 2 ECE/CS 314
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l14_handouts_4up - Announcements Homework 3b (Verilog...

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