{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

Web_Answers_12 - Unit 12 Problem Solutions 12.1 Consider 3...

This preview shows pages 1–2. Sign up to view the full content.

Unit 12 Problem Solutions 12.1 Consider 3 × Y = Y + Y + Y , that is, we need to add Y to itself 3 times. First, clear the accumulator before the first rising clock edge so that the X -register is 000000. Let the Ad pulse be 1 for 3 rising clock edges and let the Y register contain the desired number ( y 5 y 4 y 3 y 2 y 1 y 0 ) which is to be added three times. The timing diagram is on FLD p. 650. Note: ClrN should go to 0 and back to 1 before the first rising clock edge. Ad should be 1 before the same clock edge. However, it does not matter in what order, that is, Ad could go to 1 before ClrN returns to 1, or even before it goes to 0. 12.2 Serial input connected to D 0 for left shift. Sh = 0, L = 1 causes a left shift. Sh = 1, L = 1 or 0 causes a right shift 12.3 Clock 4-bit Parallel In Parallel Out Shift Register Serial Out SI SH Ld Q 3 Q 2 Q 1 Q 0 D 3 D 2 D 1 D 0 See FLD p. 650 for solution. Present State D C B A Next State D + C + B + A + Flip-Flop Inputs T D T C T B T A 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 0 1 1 1

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

Page1 / 4

Web_Answers_12 - Unit 12 Problem Solutions 12.1 Consider 3...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online