Web_Answers_12 - Unit 12 Problem Solutions 12.1 Consider 3...

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Unit 12 Problem Solutions 12.1 Consider 3 × Y = Y + Y + Y , that is, we need to add Y to itself 3 times. First, clear the accumulator before the ±rst rising clock edge so that the X -register is 000000. Let the Ad pulse be 1 for 3 rising clock edges and let the Y register contain the desired number ( y 5 y 4 y 3 y 2 y 1 y 0 ) which is to be added three times. The timing diagram is on FLD p. 650. Note: ClrN should go to 0 and back to 1 before the ±rst rising clock edge. Ad should be 1 before the same clock edge. However, it does not matter in what order, that is, Ad could go to 1 before ClrN returns to 1, or even before it goes to 0. 12.2 Serial input connected to D 0 for left shift. Sh = 0, L = 1 causes a left shift. Sh = 1, L = 1 or 0 causes a right shift 12.3 Clock 4-bit Parallel In Parallel Out Shift Register Serial Out SI SH Ld Q 3 Q 2 Q 1 Q 0 D 3 D 2 D 1 D 0 See FLD p. 650 for solution. Present State D C B A Next State D + C + B + A + Flip-Flop Inputs T D T C T B T A 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 0 1 1 1
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This note was uploaded on 09/03/2008 for the course EE 316 taught by Professor Brown during the Fall '08 term at University of Texas at Austin.

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Web_Answers_12 - Unit 12 Problem Solutions 12.1 Consider 3...

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