Chapter 4 The Processor_Part III [Compatibility Mode] -...

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° Both load and store instructions shows that information must be placed in a pipeline register ° Each logic component of the datapath can be used only within a single pipeline stage ° Otherwise->structural hazard ° Pipelining can be difficult to understand Many instructions are simultaneously executing in a ° single datapath in every clock cycle ° Two basic styles of pipelining figures ° Multiple-clock-cycle ° Single-clock-cycle Chapter 4 — The Processor — 1
Multi-Cycle Pipeline Diagram ° Form showing resource usage Chapter 4 — The Processor — 2
Multi-Cycle Pipeline Diagram ° Traditional form Chapter 4 — The Processor — 3
° Single-clock-cycle pipeline diagram ° State of the entire datapath during a single clock cycle ° Used to show the details of what is happening within the pipeline during each clock cycle ° Multiple-clock-cycle pipeline diagram ° to give overviews of pipelining situations Chapter 4 — The Processor — 4
Single-Cycle Pipeline Diagram ° State of pipeline in a given cycle Chapter 4 — The Processor — 5
Pipelined Control (Simplified) Chapter 4 — The Processor — 6
Pipelined Control ° Control signals derived from instruction ° As in single-cycle implementation Chapter 4 — The Processor — 7
Pipelined Control Chapter 4 — The Processor — 8
4.7 Data Hazards in ALU Instructions ° Consider this sequence: sub $2 , $1,$3 and $12, $2 ,$5 or $13,$6, $2 add $14, $2 , $2 Chapter 4 — The Processor — 9 sw $15,100( $2 ) ° We can resolve hazards with forwarding ° How do we detect when to forward?
Dependencies & Forwarding Chapter 4 — The Processor — 10

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